Use this dialog box to specify the required maximum delay for timing paths in the current design.
SmartTime automatically derives the individual maximum delay targets from clock waveforms and port input or output delays. So the maximum delay constraint is a timing exception. This constraint overrides the default single cycle timing relationship for one or more timing paths. This constraint also overrides a multiple cycle path constraint.
To open the Set Maximum Delay Constraint dialog box (shown below) from the SmartTime Constraints Editor, choose Actions > Constraints > Max Delay.
Set Maximum Delay Constraint Dialog Box
Specifies a floating point number in nanoseconds that represents the required maximum delay value for specified paths.
If the path starting point is on a sequential device, SmartTime includes clock skew in the computed delay.
If the path starting point has an input delay specified, SmartTime adds that delay value to the path delay.
If the path ending point is on a sequential device, SmartTime includes clock skew and library setup time in the computed delay.
If the ending point has an output delay specified, SmartTime adds that delay to the path delay.
Specifies the starting points for max delay constraint. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.
Specifies the through points for maximum delay constraint.
Specifies the ending points for maximum delay constraint. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.
Enables you to provide comments for this constraint.