Use this dialog box to specify the paths that take multiple clock cycles in the current design.
Setting multiple cycle paths constraint overrides the single cycle timing relationships between sequential elements by specifying the number of cycles that the data path must have for setup or hold checks.
Note: The false path information always takes precedence over multiple cycle path information. A specific maximum delay constraint overrides a general multiple cycle path constraint.
To open the Set Multicycle Constraint dialog box (shown below) from the SmartTime Constraints Editor, choose Actions > Constraints > Multicycle.
Set Multicycle Constraint Dialog Box
Specifies an integer value that represents a number of cycles the data path must have for setup or hold check.
Specifies the starting points for the multiple cycle constraint. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.
Specifies the through points for the multiple cycle constraint.
Specifies the ending points for the multiple cycle constraint. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.
Enables you to provide comments for this constraint.