Use this dialog box to apply output delay constraints. This constraint defines the output delay of an output relative to a clock.
To open the Set Output Delay Constraint dialog box (shown below) from the SmartTime Constraints Editor, choose Actions > Constraints > Output Delay.
Set Output Delay (Show By: Clock-to-Output) Dialog Box
Specifies a list of output ports in the current design to which the constraint is assigned. You can apply more than one port.
Specifies the clock reference to which the specified Clock-to-Output is related.
Indicates the clock edge of the launched edge.
Specifies the delay for the longest path from the clock port to the output port. This constraint includes the combinational path delay from output of the launched edge to the output port.
Specifies the delay for the shortest path from the clock port to the output port. This constraint includes the combinational path delay from output of the launched edge to the output port.
Enables you to provide comments for this constraint.
Set Output Delay (Show By: Output Delay) Dialog Box
Specifies a list of output ports in the current design to which the constraint is assigned. You can apply more than one port.
Specifies the clock reference to which the specified output delay is related.
Indicates the launching edge of the clock.
Specifies the delay for the longest path from the specified output to the captured edge. This represents a combinational path delay to a register outside the current design plus the library setup time.
Specifies the delay for the shortest path from the specified output to the captured edge. This represents a combinational path delay to a register outside the current design plus the library hold time.
Enables you to provide comments for this constraint.