Before you can start Precision RTL you must add it to your project profile.
To start Precision RTL to run synthesis:
In Libero, right-click the HDL file in the File Manager or the top-level schematic for mixed schematic-HDL designs in the Design Hierarchy, and select Synthesize. Precision starts.
(Optional) Click Setup Design to enter clock frequency, input delays and output delays.
(Optional) Click Constraint if you want to import a constraint file (*.sdf).
Click Compile if you want to compile the design first.
If compile runs without error, click Synthesize to optimize the design for your target technology. To investigate errors in the log window, click the red error icon next to the error. An HDL Text Editor opens and the part of the HDL text which is the source of the error is automatically highlighted for you to modify. Click Save to save the changes you have made to the HDL text. Rerun Synthesis to get a successful run.
Click Synthesize. Precision RTL runs compile and then synthesizes your design.
The synthesized netlist (EDIF format) is visible under Implementation Files in the Libero File Manager tab.
From the File menu, select Exit to close Precision RTL. A dialog box asks you if you would like to save any settings that you have made while in Precision. Click Yes to save the Precision project file (*.psp).