In the Libero IDE, right-click the HDL file in the File Manager, or the top-level schematic for mixed schematic-HDL designs in the Design Hierarchy, and select Synthesize. Synplify starts and loads the appropriate design files, with a few pre-set default values.
From Synplify’s Project menu, choose Implementation Options.
Set your specifications and click OK.
Deactivate synthesis
of the defparam statement. The defparam statement is only for simulation
tools and is not intended for synthesis. Embed the defparam statement
in between translate_on and translate_off synthesis directives as
follows :
/* synthesis translate_off */
defparam M0.MEMORYFILE = "meminit.dat"
/*synthesis translate_on */
// rest of the code for synthesis
Click the RUN button. Synplify compiles and synthesizes the design into an EDIF, *.edn, file. Your EDIF netlist is then automatically translated by Libero into an HDL netlist. The resulting *edn and *.vhd files are visible in the File Manager, under Implementation Files.
Should any errors appear after you click the Run button, you can edit the file using the Synplify editor. Double-click the file name in the Synplify window showing the loaded design files. Any changes you make are saved to your original design file in Libero.
From the File menu, choose Exit to close Synplify. A dialog box asks you if you would like to save any settings that you have made while in Synplify. Click Yes.
Note: See the Actel Attribute and Directive Summary in the Synplicity online help for a list of attributes related to Actel devices.
To add a clock constraint in Synplicity, you must add "n:<net_name>" in your SDC file. If you put the net_name only, it does not work.