Actel Timer uses two different timing models, pin-to-pin and input-to-input. The first type uses a pin-to-pin timing model, because Timer reports a pin-to-pin delay. The second type uses an “input-to-input” timing model, because Timer reports the delays from an input gate to the input of the next gate by lumping the gate and net delays together.
ACT1, ACT2, ACT3, 3200DX, MX, and SX devices use the input-to-input timing model, while the SX-A, RTSX-S, eX, Axcelerator, ProASIC, ProASICPLUS, and ProASIC3/E families use the pin-to-pin timing model. Some timing analysis features are specific to the different timing models; exceptions are noted in the help.
The delay for pin-to-pin devices is reported until the input pins of the registers. Therefore, setup time is not included in the delay. However, the register setup and hold, as well as the clock skew, are taken into account during the analysis of setup check and hold check when identifying timing violations. Setup, hold, and clock skew are also taken into account during clock frequency estimation.
For information on the setup and hold process in Timer, see the Expanded Paths window. It enables you to view clock network insertion delay and clock skew information.
The timing tool sees a PLL as a register and a clock generator. Any clock output port in a PLL is a potential clock (and appears in the list of potential clocks for the design). Like all other potential clocks, you can constrain these PLL output clocks by setting any clock constraint independently. The input clock of the PLL on which you set the constraint is not the clock input port of the PLL but the clock driving this clock input port. The driving clock will be a Primary port of the design, a register’s output, or another PLL’s output.
By default, when you set a clock constraint on the clock source connected to the clock input of the PLL, Timer automatically computes the clock constraints on the outputs of the PLL (according to the PLLs configuration). Thus, the value of the clock output is equivalent to the clock input multiplied, divided, or shifted by the value of your static configuration.
If you specify a clock constraint for the output clock(s), the PLL ignores the static configuration value and delivers a clock frequency according to your constraints. Timer reports this value accurately. In addition, if you remove your constraints on the output clock(s), the Timer tool recalculates your output frequency according to your static configuration value. For more information on generating PLLs and their logic characteristics, please refer to the ACTgen Macros Reference Guide in the online help or in .pdf format.
Note: For ProASICPLUS and ProASIC3/E families, the PLL is considered as a register only; there is no output clock computation. Apply constraints on the output of the PLL.
The Timer tool displays blocks of RAM and FIFO as a single “black box,” (you have as many black boxes as you have instantiations of RAMs and FIFOs in your design). Thus, if you construct a RAM or FIFO cell out of several RAM blocks, Timer sees and treats the cell as a single black box. Timer does not display timing information within individual black boxes, because all the delays are reported using the interface of the RAM. Timer displays timing information between black boxes and other logic in the design.
Timer treats RAMs and FIFOs as registers, and like any register, they have clock signals. For more information about RAMs and FIFOs, please refer to the ACTgen Macros Reference Guide, in the online help or in .pdf format.
FIFO: Timer displays the paths to the FIFO flags depending on their clock. Timer shows paths to Empty and Almost Empty with respect to the Read clock; paths to Full and Almost Full are displayed with respect to the Write clock. Check the datasheet for your device to determine whether the FIFO flags change with the Rising or Falling edge of the clock.