Timer is Actel’s static timing analysis tool. Timing analysis is a convenient and thorough method of analyzing, debugging, and validating the timing performance of a design. This is achieved by breaking down the design into sets of paths. Delays for each path are then calculated and every path is checked for timing violations.
You can only use Timer after you open a compiled design (*.adb file), or after compiling a netlist in designer. If you invoke Timer before compiling your netlist, Designer guides you through the compile process.
There are three ways to start Timer:
Choose Timer from the Tools menu.
Click the Timer icon in Designer’s toolbar.
Click the Timer button in Designer’s design flow.