Because a design’s performance is often measured by the clock frequency, determining the clock frequency is the most common use of static timing analysis.
To obtain a specific clock frequency:
Click the Summary tab in the Timer window.
Select a clock from the Select Clock list. The selected clock becomes your current clock. The frequency is displayed under the speedometer.
The clocks listed in the drop-down menu are defined as signals which drive the clock or gated input of two or more adjacent registers. For pin-to-pin delay families, one register is enough to have the clock listed as a potential clock. Timer does not support virtual clocks.
In frequency calculations, values for latency is assumed to be 0, the duty cycle is 50%, and the starting clock edge is rising. (You can set the duty cycle in the Clocks tab.) For pin-to-pin timing model families, Timer takes into account the register setup and the clock skew when estimating the maximum clock frequency. For more information on calculating delays, refer to Calculating Delays.
Clock frequency should be the inverse of reg-reg delay plus setup time. However, this is not true with clock skew.
For pin-to-pin timing model families (SX-A, eX, Axcelerator, and ProASIC, ProASICPLUS, and ProASIC3/E), Timer takes into account the register setup and the clock skew when estimating the maximum clock frequency.
Your clock frequency is: 1 / (path delay + setup - skew) if both registers are sensitive to the same clock edge.