/******************************************************************************/
/* */
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved. */
/* */
/* The contents of this file are subject to the current version of the Sun */
/* Community Source License, microSPARCII ("the License"). You may not use */
/* this file except in compliance with the License. You may obtain a copy */
/* of the License by searching for "Sun Community Source License" on the */
/* World Wide Web at http://www.sun.com. See the License for the rights, */
/* obligations, and limitations governing use of the contents of this file. */
/* */
/* Sun Microsystems, Inc. has intellectual property rights relating to the */
/* technology embodied in these files. In particular, and without limitation, */
/* these intellectual property rights may include one or more U.S. patents, */
/* foreign patents, or pending applications. */
/* */
/* Sun, Sun Microsystems, the Sun logo, all Sun-based trademarks and logos, */
/* Solaris, Java and all Java-based trademarks and logos are trademarks or */
/* registered trademarks of Sun Microsystems, Inc. in the United States and */
/* other countries. microSPARC is a trademark or registered trademark of */
/* SPARC International, Inc. All SPARC trademarks are used under license and */
/* are trademarks or registered trademarks of SPARC International, Inc. in */
/* the United States and other countries. Products bearing SPARC trademarks */
/* are based upon an architecture developed by Sun Microsystems, Inc. */
/* */
/******************************************************************************/
/***************************************************************************
****************************************************************************
***
*** Program File: @(#)add4.v
***
****************************************************************************
****************************************************************************/
// @(#)add4.v 1.1 4/8/92
//
// **************************************************************
// add4 -- 4 to 2 compression adder cell
// **************************************************************
![[Up: column1 aA]](v2html-up.gif)
![[Up: column3 aA]](v2html-up.gif)
![[Up: column3 aB]](v2html-up.gif)
![[Up: column4 aA]](v2html-up.gif)
![[Up: column5 aA]](v2html-up.gif)
![[Up: column5 aB]](v2html-up.gif)
![[Up: column5 aH]](v2html-up.gif)
![[Up: column6 aA]](v2html-up.gif)
![[Up: column6 aH]](v2html-up.gif)
![[Up: column7 aA]](v2html-up.gif)
![[Up: column7 aB]](v2html-up.gif)
![[Up: column7 aH]](v2html-up.gif)
![[Up: column7 aK]](v2html-up.gif)
![[Up: column8 aA]](v2html-up.gif)
![[Up: column8 aB]](v2html-up.gif)
![[Up: column8 aH]](v2html-up.gif)
![[Up: column9 aA]](v2html-up.gif)
![[Up: column9 aB]](v2html-up.gif)
![[Up: column9 aH]](v2html-up.gif)
![[Up: column9 aC]](v2html-up.gif)
![[Up: column9 aK]](v2html-up.gif)
![[Up: column10 aA]](v2html-up.gif)
![[Up: column10 aB]](v2html-up.gif)
![[Up: column10 aH]](v2html-up.gif)
![[Up: column10 aI]](v2html-up.gif)
![[Up: column11 aA]](v2html-up.gif)
![[Up: column11 aB]](v2html-up.gif)
![[Up: column11 aH]](v2html-up.gif)
![[Up: column11 aC]](v2html-up.gif)
![[Up: column11 aI]](v2html-up.gif)
![[Up: column11 aK]](v2html-up.gif)
... (truncated)
module add4
(s, c, cout, x1, x2, x3, x4, cin);
//prop CELLCLASS "LEAF"
//prop AREA 0.0 0.0 100.0 100.0
//prop FEEDTHROUGH "feed0" 90.0 0.0
//prop FEEDTHROUGH "feed1" 70.0 0.0
//prop FEEDTHROUGH "feed2" 50.0 0.0
//prop FEEDTHROUGH "feed3" 30.0 0.0
//prop FEEDTHROUGH "feed4" 10.0 0.0
output s
;
//prop LOCATION 60.0 0.0 60.0 0.0 "MET2"
output c
;
//prop LOCATION 40.0 0.0 40.0 0.0 "MET2"
output cout
;
//prop LOCATION 0.0 50.0 0.0 50.0 "MET1"
input x1
;
//prop LOCATION 80.0 100.0 80.0 100.0 "MET2"
input x2
;
//prop LOCATION 60.0 100.0 60.0 100.0 "MET2"
input x3
;
//prop LOCATION 40.0 100.0 40.0 100.0 "MET2"
input x4
;
//prop LOCATION 20.0 100.0 20.0 100.0 "MET2"
input cin
;
//prop LOCATION 100.0 50.0 100.0 50.0 "MET1"
// cout
or (or1, x1, x2);
or (or2, x3, x4);
and (cout, or1, or2);
// s1
xor (xor1, x1, x2);
xor (xor2, x3, x4);
xor (s1, xor1, xor2);
// S
xor (s, s1, cin);
// c1
and (and1, x1, x2);
and (and2, x3, x4);
or (c1, and1, and2);
// c
and (and3, s1, cin);
not (s1_, s1);
and (and4, s1_, c1);
or (c, and3, and4);
endmodule
This page: |
Created: | Thu Aug 19 12:00:32 1999 |
| From: |
../../../sparc_v8/ssparc/fpu/fp_fpm/rtl/add4.v
|