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/******************************************************************************/ 
/*                                                                            */ 
/* Copyright (c) 1999 Sun Microsystems, Inc. All rights reserved.             */ 
/*                                                                            */ 
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/* Community Source License, microSPARCII ("the License"). You may not use    */ 
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/******************************************************************************/ 
/***************************************************************************
****************************************************************************
***
***  Program File:  @(#)column1.v
***
****************************************************************************
****************************************************************************/

//  @(#)column1.v	1.1  4/8/92
//
// **************************************************************
//  column1 -- 2 to 2 compression for column 1.
// **************************************************************

[Up: array col1]
module column1     (
		    sum,		// compressed sum
		    carry,		// compressed carry
		    cout1,		// non-ripple carry-out
		    cin1,		// non-ripple carry-in
		    x,			// multiplicand
		    y,			// multiplier
		    pass,		// pass = {0,1}
		    fbs,		// feedback sum
		    fbc			// feedback carry
		    );
	//prop CELLCLASS "MODULE"
	//prop GENERATOR "DataPath"
	//prop TERMPLACE "BIT"

    supply0 GND;
	//prop NETTYPE "GROUND"

    output sum;
	//prop TERMPLACE "BOT"
    output carry;
	//prop TERMPLACE "BOT"
    output cout1;
	//prop TERMPLACE "LEFT"
    input  cin1;
	//prop TERMPLACE "RIGHT"
    input  [27:26] x;
	//prop TERMPLACE "TOP"
    input  [1:0] y;
	//prop TERMPLACE "LEFT"
    input pass;
	//prop TERMPLACE "LEFT"
    input fbs;
	//prop TERMPLACE "BOT"
    input fbc;
	//prop TERMPLACE "BOT"

    wire  [3:0] p;		// partial products
    wire  cin1;
    wire  s;			// internal sum's
    wire  pass;
    wire  fbs;
    wire  fbc;

    pproduct21 pA (
	    p[3:0],
	    x[27:26],
	    y[1:0],
	    pass,
	    fbs,
	    fbc
	    );
	    //prop TERMPLACE "POS=0"
	       
    add4 aA (
	    sum,
	    carry,
	    cout1,
	    p[0],
	    p[1],
	    p[2],
	    p[3],
	    cin1
	    );
	    //prop TERMPLACE "POS=1"

endmodule
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This page: Created:Thu Aug 19 12:02:31 1999
From: ../../../sparc_v8/ssparc/fpu/fp_fpm/rtl/column1.v

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