fork
				rd_dat = # ( access_time_from_cas_85_100 * `CYCLETIME) rd_dat_tmp ;
				rd_par = # ( access_time_from_cas_85_100 * `CYCLETIME) rd_par_tmp ;
			join
		`SPEED125:
			fork
				rd_dat = # ( access_time_from_cas_125 * `CYCLETIME) rd_dat_tmp ;
				rd_par = # ( access_time_from_cas_125 * `CYCLETIME) rd_par_tmp ;
			join
		`SPEED150:
			fork
				rd_dat = # ( access_time_from_cas_150 * `CYCLETIME) rd_dat_tmp ;
				rd_par = # ( access_time_from_cas_150 * `CYCLETIME) rd_par_tmp ;
			join
		`SPEED175:
			fork
				rd_dat = # ( access_time_from_cas_175 * `CYCLETIME) rd_dat_tmp ;
				rd_par = # ( access_time_from_cas_175 * `CYCLETIME) rd_par_tmp ;
			join
		`SPEED200:
			fork
				rd_dat = # ( access_time_from_cas_200 * `CYCLETIME) rd_dat_tmp ;
				rd_par = # ( access_time_from_cas_200 * `CYCLETIME) rd_par_tmp ;
			join
		endcase

/* If we use DRAM spec value directly, we don't need to have different speed cases, just use the following for all */
/*******************************************************************************************************************
		fork
			rd_dat = # ( access_time_from_cas) rd_dat_tmp ;
                        rd_par = # ( access_time_from_cas) rd_par_tmp ;
                join
********************************************************************************************************************/


//             $display("Cycle: %g read_cyc: Index: %h rd_dat: %h rd_par: %h", $stime, Index, rd_dat, rd_par);
		ParUpdateFlag_FPM = `NEGATED;
		if (rd_par[1] == 1'b0) begin
			//$display("par1_valid = 0");
			rd_par[1] = 1'b1; 
			rd_par[0] = ^rd_dat[31:0];
			ParUpdateFlag_FPM = `ASSERTED;
			end
		if (rd_par[9] == 1'b0) begin
			//$display("par0_valid = 0");
			rd_par[9] = 1'b1;
			rd_par[8] = ^rd_dat[63:32];
			ParUpdateFlag_FPM = `ASSERTED;
			end
		if (ParUpdateFlag_FPM == `ASSERTED) begin
			//$display("parity ram being updated");
			$mem_write(Msystem.TheRam.parHandle, Index, 8'b00000011, rd_par);
			//$display("par_write, rd_dat: %h  rd_par: %h", rd_dat, rd_par);
			end


		// Until we model the parity RAMs, just generate
		//     even parity over the data we've just read.
		// {rd_par[8], rd_par[0]} = {^rd_dat[63:32], ^rd_dat[31:0]} ;

                end /* else */
                wait  ( CasFlag == `NEGATED )  ;
            end /* of  wait ( CasFlag == `ASSERTED.... */
end // of always.

/*
always @(negedge FPM_cas_l[3] or negedge FPM_cas_l[2] or negedge FPM_cas_l[1] or negedge FPM_cas_l[0]) begin
	if ((FPM_ras_l != 8'hff) && FPM_mwe_l) begin
		FPM_ram_output = 1'b1;
	end
end

always @(posedge FPM_cas_l[3] or posedge FPM_cas_l[2] or posedge FPM_cas_l[1] or posedge FPM_cas_l[0]) begin
	if (FPM_ram_output) begin
		FPM_ram_output = # RAM_DELAY_FPM 1'b0 ;
	end
end
*/
// Changed as follows YS.
always @(negedge FPM_moe_l) begin
        if (FPM_ras_l != 8'hff) begin
                FPM_ram_output = 1'b1;
        end
end

always @(posedge FPM_moe_l) begin
        if (FPM_ram_output) begin
                FPM_ram_output = # RAM_DELAY_FPM 1'b0 ;
        end
end


task mem_dump;
	input [27:3] addr;
	input [31:0] data;
	input	odd_word;
	begin
		if (~mem_trace) begin
			if (mem_mcd != 0) begin
				$fclose(mem_mcd);
				mem_mcd = 0;
			end
		end
		else begin
			if (mem_mcd == 0)
				mem_mcd = $fopen({Mclocks.working_dir,"/mem_trace.v"});
			if (mem_mcd != 0) begin
				if (odd_word) 
					$fdisplay(mem_mcd, "0x%h	0x%h	%g",{4'b0, addr[27:03],3'b100},data,Mclocks.cycle_count);
				else
					$fdisplay(mem_mcd, "0x%h	0x%h	%g",{4'b0, addr[27:03],3'b000},data,Mclocks.cycle_count);
			end 
			else $display( "dram: unable to open 'mem_trace.v'") ;
         	end
	end
endtask
endmodule