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Xilinx Answer #8428 : JTAG - Is the JTAG functionality available if GTS is asserted in XC4000 designs?
Xilinx Answer #5216 : Difference in E and EX libraries
Xilinx Answer #4560 : 3000, 4000E/X, 5200, 9500/X: Measuring die temperature
Xilinx Answer #4453 : XC4000E: What is the maximum continuous sourcing current?
Xilinx Answer #3273 : SPARTAN: Explanation of speedgrades in Spartan
Xilinx Answer #2748 : FPGA Configuration: ALL I/O (including DONE) Tristate during configuration.
Xilinx Answer #2632 : XC3000A, XC4000/E/X: How to implement flip-flops with both asynchronous preset and clear/reset inputs
Xilinx Answer #2098 : FPGA Configuration: What are the thresholds for the Configuration Pins?
Xilinx Answer #1912 : 4000E/EX/XL/XV: Bare die, what should the backside (substrate) connected to?
Xilinx Answer #1908 : Global reset polarity in 2K, 3K, 4K/E/EX, 5K, 7K, and 9K devices
Xilinx Answer #1773 : xc4000e: dp-ram:xnfprep gives segmentation fault, core dump
Xilinx Answer #1279 : JTAG - Does data appear on TDO and DOUT during JTAG configuration of 4k/5k/Spartan families?
Xilinx Answer #1242 : LogiCORE PCI: Does the XC4000E meet capacitance and inductance specs for PCI?
Xilinx Answer #1146 : **Obsolete Solution**: DATA BOOK: 1994 3rd Edition: Error in boundary scan order for 4010 BG255 on page 2-62
Xilinx Answer #1109 : 96 DATA BOOK: 4025ehq208 not found in partlist.xct
Xilinx Answer #1100 : XC4000E: What is state of RAMs upon power-up/configuration?
Xilinx Answer #993 : JTAG - /PROGRAM held low in FPGA's limits boundary scan instruction set
Xilinx Answer #940 : JTAG - How to configure a XC4000/XC5200/Spartan families via Boundary Scan
Xilinx Answer #860 : XC4000E: 4025E pinout update for the MQ240, HQ240, and HQ304 packages
Xilinx Answer #765 : "Extra" RAM Components in ViewLogic 4KE Libraries, no license found for symbol
Xilinx Answer #760 : FPGA Configuration: XC4000E won't configure in socket designed for XC4000?
Xilinx Answer #492 : FPGA Configuration: Minimum pulse width for PROG to reconfigure an FPGA.
Xilinx Answer #239 : JTAG - Avoiding inadvertent activation of boundary scan in Xilinx devices with Pull-up resistors
Xilinx Answer #170 : XC4000 JTAG - Can boundary scan pins be used for JTAG and standard input/output at the same time?