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EDIF 2.0.0 naming conventions and translation of escaped Verilog names to EDIF
Record #1554
Problem Title:
EDIF 2.0.0 naming conventions and translation of escaped Verilog names to EDIF
Problem Description:
Urgency: standard
General Description:
According to the EDIF 2 0 0 Reference, a valid EDIF identifier
may only contain alphanumeric or underscore characters. In
other words, the only legal characters in an EDIF identiffier
are:
<input> a-z, A-Z, 0-9, _
</input>
If the first character of the identifier is not an alphabetic
character, it must be prefixed by an ampersand ("&").
In other words, the construct for an EDIF identifier can be
described as:
alpha | '&' { alpha | digit | '_' }
Note that forward and back slashes are not legal in an EDIF
identifier.
When the Cadence SIR2EDF encounters escaped Verilog names
(please refer to (Xilinx Solution 2533))
"\L/R " is mapped by the Cadence SIR2EDF netlister to
"&_l_r_".
The SIR2EDF netlister also creates a map file, which
shows that the identifier "&_l_r_" is mapped to "\l/r ".
Such conversions of back and forward slashes may be fairly
common in netlists generated by NGD2VER if user-specified
names do not conform to Verilog naming restrictions.
Solution 1:
End of Record #1554 - Last Modified: 04/06/98 14:17 |
