Answers Database
SYNPLIFY: How to specify a port on a black_box is a clock using the syn_isclock attribute?
Record #1561
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: How to specify a port on a black_box is a clock using the syn_isclock attribute?
Problem Description:
Urgency: Standard
General Description: How to specify a port on a black_box
is a clock using the syn_isclock attribute?
The syn_isclock attribute specifies that a port on a black box
is a clock even though Synplify doesn't recognize the port
name as a clock. Recognized names are: clk, rclk and wclk.
Please see (Xilinx Solution 2713) for declaring a black_box
within Synplify.
Solution 1:
VHDL
----
-- Sub-block A description
library synplify;
use synplify.attributes.all;
library ieee;
use ieee.std_logic_1164.all;
entity hier_bba_ex1 is
port (
myclk, rst, a, b : in std_logic;
A_out : out std_logic);
attribute syn_isclock of myclk : port is true;
end entity;
architecture XILINX of hier_bba_ex1 is
attribute black_box of XILINX : architecture is true;
begin
end XILINX;
-- Sub-block B description
library synplify;
use synplify.attributes.all;
library ieee;
use ieee.std_logic_1164.all;
entity hier_bbb_ex1 is
port (
myclk, rst, c, d, A_out : in std_logic;
z : out std_logic);
attribute syn_isclock of myclk : port is true;
end entity;
architecture XILINX of hier_bbb_ex1 is
attribute black_box of XILINX : architecture is true;
begin
end XILINX;
-- Top level description
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
myclk, rst, a, b, c, d : in std_logic;
z : out std_logic);
end entity;
architecture XILINX of top is
component hier_bba_ex1
port(myclk, rst, a, b : in std_logic;
A_out : out std_logic);
end component;
component hier_bbb_ex1
port(myclk, rst, c, d, A_out : in std_logic;
z : out std_logic);
end component;
signal A_out : std_logic;
begin
U1 : hier_bba_ex1
port map (myclk, rst, a, b, A_out);
U2 : hier_bbb_ex1
port map (myclk, rst, c, d, A_out, z);
end XILINX;
Solution 2:
Verilog
-----
/**** Sub-block A black box ****/
module block_A (myclk, rst, a, b, A_out) /* synthesis black_box */;
input myclk /* synthesis syn_isclock = 1 */;
input rst, a, b;
output A_out;
endmodule
/**** Sub-block B black box ****/
module block_B (myclk, rst, c, d, A_out, z) /* synthesis black_box */;
input myclk /* synthesis syn_isclock = 1 */;
input rst, c, d, A_out;
output z;
endmodule
/**** Top level description ****/
module example (myclk, rst, a, b, c, d, z);
input myclk, rst, a, b, c, d;
output z;
wire A_out;
block_A U1 (myclk, rst, a, b, A_out);
block_B U2 (myclk, rst, c, d, A_out, z);
endmodule
End of Record #1561 - Last Modified: 06/24/99 14:51 |
