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SYNPLIFY: How to instantiate LUT primitives in HDL for Virtex?
Record #1992
Product Family: Software
Product Line: Synplicity
Product Part: Synplify
Product Version: 5.0
Problem Title:
SYNPLIFY: How to instantiate LUT primitives in HDL for Virtex?
Problem Description:
Urgency: Standard
General Description:
How to instantiate LUT primitives in HDL for Virtex using
Synplicity's Synplify?
You can instantiate the LUT* cells by using the Xilinx family
library supplied with Synplify. Please see (Xilinx Solution 244) for
details of instantiating Xilinx-specific cells.
LUT1, LUT2, LUT3, and LUT4 are, respectively, 1-, 2-, 3-, and
4-bit look-up-tables (LUTs) with general output (O).
A mandatory INIT attribute, with an appropriate number of
hexadecimal digits for the number of inputs, must be
attached to the LUT to specify its function.
LUT1 provides a look-up-table version of a buffer or inverter.
NOTE: Tested with Synplify 5.1.4
Solution 1:
VHDL
----
library ieee;
use ieee.std_logic_1164.all;
library virtex;
use virtex.components.all;
entity lut_ex is
port (
LUT1_IN, LUT2_IN : in std_logic_vector(1 downto 0);
LUT1_OUT, LUT2_OUT : out std_logic_vector(1 downto 0));
end entity lut_ex;
architecture XILINX of LUT_EX is
component LUT1
generic (INIT: std_logic_vector(1 downto 0) := "10");
port (O : out std_logic;
I0 : in std_logic);
end component;
component LUT2
generic (INIT: std_logic_vector(3 downto 0) := "0000");
port (O : out std_logic;
I0, I1 : in std_logic);
end component;
begin
-- LUT1 used as an inverter
U0 : LUT1 generic map (INIT => "01")
port map (O => LUT1_OUT(0), I0 => LUT1_IN(0));
-- LUT1 used as a buffer
U1 : LUT1 generic map (INIT => "10")
port map (O => LUT1_OUT(1), I0 => LUT1_IN(1));
-- LUT2 used as a 2-input AND gate
U2 : LUT2 generic map (INIT => "1000")
port map (O => LUT2_OUT(0), I1 => LUT2_IN(1), I0 => LUT2_IN(0));
-- LUT2 used as a 2-input NAND gate
U3 : LUT2 generic map (INIT => "0111")
port map (O => LUT2_OUT(1), I1 => LUT2_IN(1), I0 => LUT2_IN(0));
end XILINX;
Solution 2:
Verilog
------
`include "<synplify_install>/lib/xilinx/virtex.v"
module lut_ex (LUT1_OUT, LUT1_IN, LUT2_OUT, LUT2_IN);
input [1:0] LUT1_IN, LUT2_IN;
output [1:0] LUT1_OUT, LUT2_OUT;
// LUT1 used as an inverter
defparam U0.INIT = 2'b01;
LUT1 U0 (.O (LUT1_OUT[0]), .I0 (LUT1_IN[0]));
// LUT1 used as a buffer
defparam U1.INIT = 2'b10;
LUT1 U1 (.O (LUT1_OUT[1]), .I0 (LUT1_IN[1]));
// LUT2 used as a 2-input AND gate
defparam U2.INIT = 4'b1000;
LUT2 U2 (.O (LUT2_OUT[0]), .I1 (LUT2_IN[1]), .I0 (LUT2_IN[0]));
// LUT2 used as a 2-input NAND gate
defparam U3.INIT = 4'b0111;
LUT2 U3 (.O (LUT2_OUT[1]), .I1 (LUT2_IN[1]), .I0 (LUT2_IN[0]));
endmodule
End of Record #1992 - Last Modified: 06/30/99 13:42 |
