Answers Database
SYNPLIFY: How to instantiate Xilinx specific components in HDL?
Record #244
Problem Title:
SYNPLIFY: How to instantiate Xilinx specific components in HDL?
Problem Description:
Urgency: Standard
General Description:
How to instantiate Xilinx specific components in HDL?
Please review the following links for specific examples:
How to instantiate RAM or ROM in HDL?
Please see (Xilinx Solution 2104)
How to instantiate the STARTUP for a XC5200 design?
Please see (Xilinx Solution 3323)
How to instantiate the mode pins (MD0, MD1, MD2) in HDL?
Please see (Xilinx Solution 3496)
How to instantiate the JTAG pins (TDI, TDO, TCK, TMS) in
HDL as general I/O?
Please see (Xilinx Solution 4641)
How to instantiate BSCAN in HDL?
Please see (Xilinx Solution 2805)
How to instantiate an FMAP or HMAP (RLOC) in the
HDL code?
Please see (Xilinx Solution 3924)
How to instantiate LUT primitives in HDL for Virtex?
Please see (Xilinx Solution 1992)
Solution 1:
The Synplify Xilinx macro libraries contain pre-defined black-boxes for
the Xilinx primitives so that you can manually instantiate them into your
design.
For VHDL based designs, all one has to do is add the following
2 lines in the VHDL.
library <family>;
use <family>.components.all;
For Verilog designs, just add the <family>.v file in the source file list
along with the source design files.
Where <family> is replaced by xc3000, xc4000, or virtex. For XC5200
and XC9000 HDL designs, you must create a black-box instantiation
of the primitive since the libraries are not provided for you. Please see
(Xilinx Solution 2713) for details on how to create a black-box description.
The <family>.v and <family>.vhd files are available in the
$SYNPLICITY/lib/xilinx directory on the WS or C:\synplcty\lib\xilinx
on the PC. View these files for the list of components and its port
interface list.
End of Record #244 - Last Modified: 06/30/99 13:43 |
