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SYNPLIFY: How to a declare PULLUP/PULLDOWN in HDL (Verilog/VHDL)?
Record #2145
Problem Title:
SYNPLIFY: How to a declare PULLUP/PULLDOWN in HDL (Verilog/VHDL)?
Problem Description:
Urgency: standard
General description: How to instantiate PULLUP/PULLDOWN using
Syplicity's synplify in HDL?
Note: For CPLD devices, PULLUPs in the IOBs are not user controllable
during normal operation. These PULLUP resistors are active only during
device programming, power-up, and erase cycle.
Note: For Virtex, please see (Xilinx Solution 948) for details of Synlify 5.1.4
and earliear.
You can instantiate PULLUP/PULLDOWN cells by using the Xilinx family
library supplied with Synplify. Please see (Xilinx Solution 244) for details of
instantiating Xilinx-specific cells.
Note: Synplify 5.0.7 introduces 2 new attributes, xc_pullup and
xc_pulldown, to implement PULLUP, PULLDOWN.
Solution 1:
// IOB Pullup/Pulldown with a registered bidirectional I/O
// Using xc_pulldown/xc_pullup attributes
// Only for Synplify 5.0.7 and later
module BIDIR_EX2 (SIGA, SIGB, INA, INB, EN, CLK);
inout SIGA /* synthesis xc_pullup = 1 */;
inout SIGB /* synthesis xc_pulldown = 1 */;
input INA, INB, EN, CLK;
reg INA_INT, OUTA_INT;
reg INB_INT, OUTB_INT;
// Registered Input path
always @(posedge CLK)
begin
INA_INT = SIGA;
INB_INT = SIGB;
end
// Registered Output path with tri-state
assign SIGA = !EN ? OUTA_INT : 1'bz;
assign SIGB = !EN ? OUTB_INT : 1'bz;
always @(posedge CLK)
begin
OUTA_INT = INA_INT & INA;
OUTB_INT = INB_INT & INB;
end
endmodule
Solution 2:
// Pullup attached to a long-line
// Internal pulldown connections are illegal.
// Pulldowns are only available on I/O pads
// Include Synplify Xilinx Macro Libraries
`include "/products/synplify/lib/xilinx/xc4000.v"
module LONG_LINE_EX1 (INBUSA, EN, SIGA, OUT_SIG);
input [2:0] INBUSA, EN;
input [1:0] SIGA;
output OUT_SIG;
wire INT_SIG;
PULLUP U0 (.O (INT_SIG));
// Infer tri-state buffers
assign INT_SIG = (EN[0] == 1'b1) ? INBUSA[0] & SIGA[0] : 1'bz;
assign INT_SIG = (EN[1] == 1'b1) ? INBUSA[1] & SIGA[0] : 1'bz;
assign INT_SIG = (EN[2] == 1'b1) ? INBUSA[2] & SIGA[0] : 1'bz;
// glue logic
assign OUT_SIG = SIGA[1] ^ INT_SIG;
endmodule
Solution 3:
-- Pullup attached to a long-line
-- Internal pulldown connections are illegal.
-- Pulldowns are only available on I/O pads
library ieee, xc4000;
use ieee.std_logic_1164.all;
use xc4000.components.all; -- Include Synplify Xilinx Macro Libraries
entity LONG_LINE_EX1 is
port (INBUSA, EN : in std_logic_vector(2 downto 0);
SIGA : in std_logic_vector(1 downto 0);
OUT_SIG : out std_logic);
end LONG_LINE_EX1;
architecture XILINX of LONG_LINE_EX1 is
component PULLUP
PORT (O : out std_logic);
end component;
signal INT_SIG : std_logic;
begin
U0 : PULLUP port map (O => INT_SIG);
-- Infer tri-state buffers
INT_SIG <= INBUSA(0) and SIGA(0) when (EN(0) = '1') else 'Z';
INT_SIG <= INBUSA(1) and SIGA(0) when (EN(1) = '1') else 'Z';
INT_SIG <= INBUSA(2) and SIGA(0) when (EN(2) = '1') else 'Z';
-- glue logic
OUT_SIG <= SIGA(1) xor INT_SIG;
end XILINX;
Solution 4:
-- IOB Pullup/Pulldown with a registered bidirectional I/O
-- Using instantiated cells
library ieee, xc4000;
use ieee.std_logic_1164.all;
use xc4000.components.all; -- Include Synplify Xilinx Macro Library
entity BIDIR_EX1 is
port (SIGA, SIGB : inout std_logic;
INA, INB, EN, CLK : in std_logic);
end BIDIR_EX1;
architecture XILINX of BIDIR_EX1 is
component PULLUP
PORT ( O: out std_logic );
end component;
component PULLDOWN
PORT ( O: out std_logic );
end component;
signal INA_INT, OUTA_INT : std_logic;
signal INB_INT, OUTB_INT : std_logic;
begin
U0 : PULLUP port map (O => SIGA);
U1 : PULLDOWN port map (O => SIGB);
-- Registered Input path
process (CLK)
begin
if rising_edge(CLK) then
INA_INT <= SIGA;
INB_INT <= SIGB;
end if;
end process;
-- Registered Output path with tri-state
SIGA <= OUTA_INT when (EN = '0') else 'Z';
SIGB <= OUTB_INT when (EN = '0') else 'Z';
process (CLK)
begin
if rising_edge(CLK) then
OUTA_INT <= INA_INT and INA;
OUTB_INT <= INB_INT and INB;
end if;
end process;
Solution 5:
-- IOB Pullup/Pulldown with a registered bidirectional I/O
-- Using xc_pulldown/xc_pullup attributes
-- Only for Synplify 5.0.7 and later
library ieee, synplify;
use ieee.std_logic_1164.all;
use synplify.attributes.all; -- Define Synplify attributes
entity BIDIR_EX1 is
port (SIGA, SIGB : inout std_logic;
INA, INB, EN, CLK : in std_logic);
attribute xc_pullup of SIGA : signal is true;
attribute xc_pulldown of SIGB : signal is true;
end BIDIR_EX1;
architecture XILINX of BIDIR_EX1 is
signal INA_INT, OUTA_INT : std_logic;
signal INB_INT, OUTB_INT : std_logic;
begin
-- Registered Input path
process (CLK)
begin
if rising_edge(CLK) then
INA_INT <= SIGA;
INB_INT <= SIGB;
end if;
end process;
-- Registered Output path with tri-state
SIGA <= OUTA_INT when (EN = '0') else 'Z';
SIGB <= OUTB_INT when (EN = '0') else 'Z';
process (CLK)
begin
if rising_edge(CLK) then
OUTA_INT <= INA_INT and INA;
OUTB_INT <= INB_INT and INB;
end if;
end process;
end XILINX;
Solution 6:
// IOB Pullup/Pulldown with a registered bidirectional I/O
// Using instantiated cells
// Include Synplify Xilinx Macro Libraries
`include "/products/synplify/lib/xilinx/xc4000.v"
module BIDIR_EX1 (SIGA, SIGB, INA, INB, EN, CLK);
inout SIGA, SIGB;
input INA, INB, EN, CLK;
reg INA_INT, OUTA_INT;
reg INB_INT, OUTB_INT;
PULLUP U0 (.O (SIGA));
PULLDOWN U1 (.O (SIGB));
// Registered Input path
always @(posedge CLK)
begin
INA_INT = SIGA;
INB_INT = SIGB;
end
// Registered Output path with tri-state
assign SIGA = !EN ? OUTA_INT : 1'bz;
assign SIGB = !EN ? OUTB_INT : 1'bz;
always @(posedge CLK)
begin
OUTA_INT = INA_INT & INA;
OUTB_INT = INB_INT & INB;
end
endmodule
End of Record #2145 - Last Modified: 06/14/99 16:13 |
