Answers Database
FPGA Express 2.x: Undefined macro 'ifdef, VE-0
Record #2275
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.1.1
Problem Title:
FPGA Express 2.x: Undefined macro 'ifdef, VE-0
Problem Description:
Urgency: Standard
General Description:
If a Verilog design uses the `ifdef compiler directive, the following error will occur during
the Analyze phase:
Error: Undefined macro `ifdef at or near token "`ifdef"
(File: C:\myproj\test\ifdef.v Line: 8) (VE-0)
Solution 1:
The `ifdef directive is not supported by versions of FPGA Express up to and including 3.1.
This issue has been addressed in FPGA Express 3.2. See (Xilinx Solution 5791) for details.
End of Record #2275 - Last Modified: 08/19/99 09:30 |
