Answers Database
NGD2VER: What is needed to do Verilog simulation of 3rd party designs using Xilinx Alliance software?
Record #2432
Product Family: Software
Product Line: Cadence
Product Part: verilog
Problem Title:
NGD2VER: What is needed to do Verilog simulation of 3rd party designs using Xilinx Alliance
software?
Problem Description:
Urgency: standard
General Description:
What is needed to do Verilog simulation of 3rd party designs in the
Xilinx Alliance software?
Solution 1:
A generic Verilog HDL interface is supplied with the Xilinx Alliance software,
consisting of the NGD2VER netlister, and generic SIMPRIM-based and
UNISIM-based Verilog simulation libraries.
Simulation libraries are used at 4 stages of the FPGA implementation flow:
RTL (UNISIM), post-NGDBUILD (SIMPRIM), post-Map Timing (SIMPRIM),
and post Route Timing (SIMPRIM). Please see (Xilinx Solution 2703) for
details.
For the CPLD flow, supports simuilation at 3 points: RTL (UNISIMS),
post-NGDBUILD (SIMPRIM) and post-fitting timing (SIMPRIM).
Please see (Xilinx Solution 3167) on details of using Verilog-XL with the
Xilinx Alliance software to point to the SIMPRIM-based libraries.
End of Record #2432 - Last Modified: 06/29/99 10:49 |
