Xilinx Answer #3323 : SYNPLIFY: How to instantiate the STARTUP for a XC5200?

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SYNPLIFY: How to instantiate the STARTUP for a XC5200?

Record #3323
Product Family: Software

Product Line: Synplicity

Product Part: Synplify

Product Version: 3.0

Problem Title:
SYNPLIFY: How to instantiate the STARTUP for a XC5200?

Problem Description:

Urgency: Standard

General Description: The global reset in the 5200 uses dedicated
routing resources to reset ALL flip-flops in the device. How to
to access the reset (GR) pin on the STARTUP block in HDL?

You can instantiate STARTUP cell by using the Xilinx family
library supplied with Synplify. Please see (Xilinx Solution 244) for
details of instantiating Xilinx-specific cells.

Solution 1:

-- This will work for XC5200, though the reset signal on the startup
-- block is labeled GR. Synplify will map GSR signal name to GR in
-- the netlist.

library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;

entity use_gr is
    port (
      reset : in STD_LOGIC
      );
end use_gr;

architecture xilinx of use_gr is

begin

-- the signal reset initializes all registers using the
-- global STARTUP signal
U1 : STARTUP port map (GSR => reset);

end xilinx;

Solution 2:

// This will work for XC5200, though the reset signal on the startup
// block is labeled GR. Synplify will map GSR signal name to GR in
// the netlist.

`include "/products/synplify.ver3_0/lib/xilinx/xc4000.v"

module use_gr (reset);
input reset;

// the signal reset initializes all registers using the
// global STARTUP signal
STARTUP U1 (.GSR (reset));

endmodule

End of Record #3323 - Last Modified: 06/22/99 16:10

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