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SYNPLIFY: How to instantiate the mode pins (MD0, MD1, MD2) in HDL (Verilog/VHDL)?
Record #3496
Problem Title:
SYNPLIFY: How to instantiate the mode pins (MD0, MD1, MD2) in HDL (Verilog/VHDL)?
Problem Description:
Urgency: Standard
General Description: How to instantiate the mode pins (MD0, MD1, MD2)
for Synplicity's Synplify?
Note: This works for synplify 3.0b and above
You can instantiate the mode pin cells by using the Xilinx family
library supplied with Synplify. Please see (Xilinx Solution 244) for
details of instantiating Xilinx-specific cells.
Note: The ports are not listed in the top-level port list
MD0 can be used as an input pad, but it must be connected through an
IBUF to the user circuit. XC5200 devices allow an MD0 pad to be used
as an output pad; XC4000 devices do not. The IOB associated with the
MD0 pad has no flip-flop or latch. This pad is usually connected
(automatically) to the RTRIG input of the READBACK function.
MD1 can be used as a 3-state or simple output pad, but it must be
connected through an OBUF or an OBUFT to the user circuit. XC5200
devices allow an MD1 pad to be used as an input pad; XC4000 devices do
not. The IOB associated with the MD0 pad has no flip-flop or latch.
This pad is usually connected to the DATA output of the READBACK function,
and the output enable of the 3-state is connected to the RIP output of
the READBACK function.
MD2 can be used as an input pad, but it must be connected through an
IBUF to the user circuit. XC5200 devices allow an MD2 pad to be used
as an output pad; XC4000 do not. The IOB associated has no flip-flop
or latch.
Solution 1:
-- Mode Pins VHDL code
library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;
entity mode_pins is
port (
din, clk : in STD_LOGIC;
qout : out STD_LOGIC
);
end mode_pins;
architecture xilinx of mode_pins is
signal MD0_I, MD1_O, MD2_I : STD_LOGIC;
signal MD0_O, MD1_I, MD2_O : STD_LOGIC;
begin
U1: MD0 port map (I =>MD0_I);
U2: MD1 port map (O =>MD1_O);
U3: MD2 port map (I =>MD2_I);
U4: IBUF port map (I => MD0_I, O => MD0_O);
U5: OBUF port map (I => MD1_I, O => MD1_O);
U6: IBUF port map (I => MD2_I, O => MD2_O);
process (clk)
begin if (clk'event and clk = '1')
then qout <= din;
end if;
end process;
-- token logic
MD1_I <= MD0_O and MD2_O;
end xilinx;
Solution 2:
// Mode pins Verilog code
`include "/products/synplify.ver3_0b/lib/xilinx/xc4000.v"
module mode_pins (din, clk, qout);
input din, clk;
output qout;
reg qout;
wire MD0_I, MD1_O, MD2_I;
wire MD0_O, MD1_I, MD2_O;
MD0 U1 (.I (MD0_I));
MD1 U2 (.O (MD1_O));
MD2 U3 (.I (MD2_I));
IBUF U4 (.I (MD0_I), .O (MD0_O));
OBUF U5 (.I (MD1_I), .O (MD1_O));
IBUF U6 (.I (MD2_I), .O (MD2_O));
always @(posedge clk)
qout <= din;
// token logic
assign MD1_I = MD0_O & MD2_O;
endmodule
End of Record #3496 - Last Modified: 06/22/99 16:13 |
