Answers Database
FPGA Express 2.x, 3.x: Constraints Editor will not allow assignment of more than 4 BUFGs
Record #4200
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Problem Title:
FPGA Express 2.x, 3.x: Constraints Editor will not allow assignment of more than 4 BUFGs
Problem Description:
Urgency: Standard
When using Express 2.x to target an XC4000 series or Spartan device, the
Express Constraints Editor will not allow the assignment of more than four
global clock buffers to signals. The devices will allow up to eight clock
buffers to be used.
Solution 1:
The solution is to instantiate all the desired clock buffers in your HDL code.
See (Xilinx Solution 3980) for examples in VHDL.
See (Xilinx Solution 3999) for examples in Verilog.
End of Record #4200 - Last Modified: 12/02/99 13:48 |
