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SYNPLIFY: How to instantiate the JTAG pins (TDI, TDO, TCK, TMS) in HDL as general I/O?
Record #4641
Problem Title:
SYNPLIFY: How to instantiate the JTAG pins (TDI, TDO, TCK, TMS) in HDL as general I/O?
Problem Description:
Urgency: Standard
General Description: How to instantiate the mode pins (TDI, TDO, TCK,
TMS) for Synplicity's Synplify?
You can instantiate the JTAG pin cells by using the Xilinx family
library supplied with Synplify. Please see (Xilinx Solution 244) for
details of instantiating Xilinx-specific cells.
Note: See (Xilinx Solution 2805) for information on how to instantiate
BSCAN in HDL.
After configuration, if boundary scan is not used, the TMS, TCK, and
TDI pads are unrestricted and can be used as user I/O pads, and the
TDO pad can be used as a bidirectional 3-state I/O pad. Please see
(Xilinx Solution 1356) for details.
Also, this functionality is only valid in the 4000E/X, Spartan, and
5200 families of FPGA's.
Note: The ports are not listed in the top-level port list
Solution 1:
-- JTAG Pins VHDL code
library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;
entity jtag_pins is
port ( din, clk : in STD_LOGIC;
qout : out STD_LOGIC);
end jtag_pins;
architecture xilinx of jtag_pins is
attribute black_box : boolean;
component TDI
port (I : out STD_LOGIC);
end component;
component TCK
port (I : out STD_LOGIC);
end component;
component TMS
port (I : out STD_LOGIC);
end component;
component TDO
port (O : in STD_LOGIC);
end component;
component IBUF
port (I : in STD_LOGIC;
O : out STD_LOGIC);
end component;
component OBUF
port (I : in STD_LOGIC;
O : out STD_LOGIC);
end component;
signal TCK_I, TDI_I, TMS_I, TDO_I : STD_LOGIC;
signal TCK_O, TDI_O, TMS_O, TDO_O : STD_LOGIC;
begin
U1 : TDI port map (I => TDI_I);
U2 : TCK port map (I => TCK_I);
U3 : TMS port map (I => TMS_I);
U4 : TDO port map (O => TDO_O);
U5 : IBUF port map (I => TDI_I, O => TDI_O);
U6 : IBUF port map (I => TCK_I, O => TCK_O);
U7 : IBUF port map (I => TMS_I, O => TMS_O);
U8 : OBUF port map (I => TDO_I, O => TDO_O);
-- User application insert here
process (clk)
begin
if (clk'event and clk = '1') then
qout <= TDI_O xor TCK_O xor TMS_O;
end if;
end process;
TDO_I <= din;
end xilinx;
Solution 2:
// JTAG pins Verilog code
`include "/products/synplify/lib/xilinx/xc4000.v"
module jtag_pins (din, clk, qout);
input din, clk;
output qout;
reg qout;
wire TCK_I, TDI_I, TMS_I, TDO_I;
wire TCK_O, TDI_O, TMS_O, TDO_O;
TDI U1 (.I (TDI_I));
TCK U2 (.I (TCK_I));
TMS U3 (.I (TMS_I));
TDO U4 (.O (TDO_O));
IBUF U5 (.I (TDI_I), .O (TDI_O));
IBUF U6 (.I (TCK_I), .O (TCK_O));
IBUF U7 (.I (TMS_I), .O (TMS_O));
OBUF U8 (.I (TDO_I), .O (TDO_O));
-- User application insert here
always @(posedge clk)
qout <= TDI_O ^ TCK_O ^ TMS_O;
assign TDO_I = din;
endmodule
End of Record #4641 - Last Modified: 06/29/99 16:50 |
