Answers Database


A1.5/F1.5 PAR - FATAL_ERROR:basnd:basndutils.c:132:1.7 - Internal Error - signal has a loop


Record #4669

Product Family: Software

Product Line: FPGA Implementation

Product Part: par

Problem Title:
A1.5/F1.5 PAR - FATAL_ERROR:basnd:basndutils.c:132:1.7 - Internal Error - signal has a loop


Problem Description:
A case has been seen where PAR fails with the error:

FATAL_ERROR:basnd:basndutils.c:132:1.7 - Internal Error - signal
has a loop, router problem? Process will terminate. Please call
Xilinx support.



Solution 1:

This error has been fixed in the M1.5 Service pack. For more information see:

    http://www.xilinx.com/techdocs/4775.htm




End of Record #4669 - Last Modified: 12/14/98 09:30

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!