Answers Database NC-VERILOG: How to compile the 1.5 Verilog Simprims, LogiBLOX, Unisims, and Coregen libraries? Record #4873 Problem Title: NC-VERILOG: How to compile the 1.5 Verilog Simprims, LogiBLOX, Unisims, and Coregen libraries? Problem Description: Urgency: Standard General Description: The Xilinx 1.5 Alliance software contains 2 types of Verilog simulation libraries and Coregen conatins one:     SIMPRIMS - Library of generic simulation primitives             Used for simulating LogiBLOX and post-Ngdbuild netlists     UNISIMS - Library of Unified component simulation models (A1.4+)             Used for RTL and post-synthesis simulation containing             Xilinx primities To perform timing or post-synthesis functional HDL simulation in the Alliance software, the Verilog Simprim models must be compiled for use in the NC Verilog simulator. If instantiated LogiBLOX and/or Unified library components are to be behaviorally simulated, the LogiBLOX and/or UNISIM libraries must be compiled, as well. Please see (Xilinx Solution 4873) on how to compile Xilinx Alliance 2.1 Verilog libraries. Solution 1: Step 1 ------ Create a library definitions file named cds.lib. The cds.lib file defines which libraries are accessible and where they are located. The file contains statements that map logical library names to their physical directory paths. Cadence provides an utility, called 'nclaunch' to setup the necessary initialization files, and to compile the Verilog source libraries. Nclaunch is available as part of the 2.1 and later releases. Otherwise, this is a manual process. The cds.lib can be created with any texteditor. The physical locations to the logical names must also be created before preceding to the next step. Use the UNIX command mkdir. For example, mkdir -p $XILINX/verilog/data/nc_verilog/simprims If you want the logical library names to be available for all designs, use INCLUDE or SOFTINCLUDE to the location of your master cds.lib file. EX: INCLUDE $CDS_INST_DIR/share/local/xilinx/cds.lib Edit $CDS_INST_DIR/share/local/xilinx/cds.lib to include DEFINE simprims_ver $XILINX/verilog/data/nc_verilog/simprims DEFINE uni3000 $XILINX/verilog/data/nc_verilog/uni3000 DEFINE uni4000e $XILINX/verilog/data/nc_verilog/uni4000e DEFINE uni4000x $XILINX/verilog/data/nc_verilog/uni4000x DEFINE uni5200 $XILINX/verilog/data/nc_verilog/uni5200 DEFINE unispartan $XILINX/verilog/data/nc_verilog/unispartan DEFINE unispartanxl $XILINX/verilog/data/nc_verilog/unispartanxl DEFINE univirtex $XILINX/verilog/data/nc_verilog/univirtex DEFINE uni9000 $XILINX/verilog/data/nc_verilog/uni9000 Step 2 ------ Create a configuration variables file called hdl.var. The hdl.var file defines variables that determine how the user environment is configured. The variable (LIB_MAP, VIEW_MAP, WORK) are used to specify the search order of the libraries and views when the elaborator resolves instances. If you want the variable settings to be available for all designs, use INCLUDE or SOFTINCLUDE to the location of your master hdl.var file. EX: INCLUDE $CDS_INST_DIR/share/local/xilinx/hdl.var Edit $CDS_INST_DIR/share/local/xilinx/hdl.var SOFTINCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var DEFINE LIB_MAP ( $LIB_MAP, \ $XILINX/verilog/data/nc_verilog/simprims_ver => simprims_ver, \ $XILINX/verilog/data/nc_verilog/uni3000 => uni3000, \ $XILINX/verilog/data/nc_verilog/uni4000e => uni4000e, \ $XILINX/verilog/data/nc_verilog/uni4000x => uni4000x, \ $XILINX/verilog/data/nc_verilog/uni5200 => uni5200, \ $XILINX/verilog/data/nc_verilog/unispartan => unispartan, \ $XILINX/verilog/data/nc_verilog/unispartanxl => unispartanxl, \ $XILINX/verilog/data/nc_verilog/univirtex => univirtex, \ $XILINX/verilog/data/nc_verilog/uni9000 => uni9000) DEFINE VIEW_MAP ( $VIEW_MAP, .vmd => vmd, .v => v) Depending on the family that you're simulating, you must edit the hdl.var file to correctly list the search order of the simulation libraries. Step 3 ------ Parse and analyze the Xilinx simulation libraries using ncvlog. SIMPRIMS -------- ncvlog -messages -work simprims_ver $XILINX/verilog/src/simprims/*.vmd UNISIMS ------- ncvlog -messages -work uni3000 $XILINX/verilog/src/UNI3000/*.v ncvlog -messages -work uni4000e $XILINX/verilog/src/UNI4000E/*.v ncvlog -messages -work uni4000x $XILINX/verilog/src/UNI4000X/*.v ncvlog -messages -work uni5200 $XILINX/verilog/src/UNI5200/*.v ncvlog -messages -work unispartan $XILINX/verilog/src/UNISPARTAN/*.v ncvlog -messages -work unispartanxl $XILINX/verilog/src/UNISPARTANXL/*.v ncvlog -messages -work univirtex $XILINX/verilog/src/UNIVIRTEX/*.v ncvlog -messages -work uni9000 $XILINX/verilog/src/UNI9000/*.v Solution 2: If you are using the UNIX OS, there are scripts availible on the Xilinx FTP site that will compile the Cadence's Affirma NC-Verilog libraries. Verilog: ftp://ftp.xilinx.com/pub/swhelp/cadence/ncv_ver_compile.tar.gz End of Record #4873 - Last Modified: 07/06/99 13:46

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