Answers Database 2.1i: Timing Analyzer: Path items counts for twr file does not match the actual path items for designs with circuit loops. Record #6392 Product Family: Software Product Line: FPGA Implementation Product Part: Timing Analyzer Product Version: 2.1i Problem Title: 2.1i: Timing Analyzer: Path items counts for twr file does not match the actual path items for designs with circuit loops. Problem Description: Urgency: Standard General Description: A design with logic loops gets analyzed in Timing Analyzer however the paths associated with logic loops are not listed. Only the 'point A' to 'point B' is listed. Solution 1: This will be fixed in the next release or service pack. More information is in "(Xilinx Solution 4367)". http://support.xilinx.com/techdocs/4367.htm End of Record #6392 - Last Modified: 06/30/99 11:03

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