Answers Database
UNISIMS/SIMPRIMS: How do I use the glbl.v module in a Verilog simulation?
Record #6537
Product Family: Software
Product Line: FPGA Implementation
Product Part: Unisim
Product Version: n/a
Problem Title:
UNISIMS/SIMPRIMS: How do I use the glbl.v module in a Verilog simulation?
Problem Description:
Urgency: Standard
How do I use the glbl.v module in a Verilog simulation?
Solution 1:
In the Alliance Series software 2.1i, the general procedure for specifying
global signals for a Verilog simulation flow involves defining the global signals
with the $XILINX/verilog/src/glbl.v module. This module allows a global
signal to be modeled as a wire in a global module.
The glbl.v module connects the global signals to the design, which is
why it is necessary to compile this module with the other design files
and load it along with the toplevel.v file or the testbench.v file for simulation.
See (Xilinx Solution 5009) on how to drive the global signals.
End of Record #6537 - Last Modified: 01/10/00 16:17 |
