Answers Database
UNISIMS/SIMPRIMS: How to drive PRLD, GSR, GR, and GTS in a Verilog simulation?
Record #5009
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngd2ver
Product Version: 2.1i
Problem Title:
UNISIMS/SIMPRIMS: How to drive PRLD, GSR, GR, and GTS in a Verilog simulation?
Problem Description:
Urgency: Standard
General description:
How to drive PRLD, GSR, GR, and GTS in a Verilog simulation?
See (Xilinx Solution 2432) regarding Verilog simulation using the Xilinx
Alliance software.
In the Xilinx software, the Verilog UNISIM library is only used in RTL
simulations of your designs. Simulation at other points in the flow use
the Verilog SIMPRIM Libraries.
For Verilog simulation, all behaviorally described (inferred) and instantiated
registers should have a common signal which asynchronously sets or
resets the register. You must toggle the global set/reset signal (GSR for
XC4000E/L/X, Spartan/XL, and Virtex designs, or GR for XC5200,
XC3000A/L, or XC3100A/L designs). Toggling the global set/reset
emulates the Power-On-Reset of the FPGA. If you do not do this, the
flip-flops and latches in your simulation enter an unknown state.
The GSR signal in XC4000E/L/X, Spartan/XL, and Virtex devices, and
the GR signal in XC5200 devices are active High. The GR signal in
XC3000A/L and XC3100A/L devices are active Low.
The global set/reset net is present in your implemented design even if
you do not instantiate the STARTUP block in your design. The function
of STARTUP is to give you the option to control the global reset net from
an external pin.
If you want to set the global set/reset pulse width so that it reflects the
actual amount of time it takes for the chip to go through the reset process
when power is supplied to it, refer to "The Programmable Logic Data Book"
for the device you are simulating. The duration of the pulse is specified as
TPOR (Power-On-Reset).
XC4000E/L/X, Spartan/XL, Virtex, and XC5200 devices also have a
global control signal (GTS) that tristates all output pins. This allows you to
isolate the actual device part during board level testing. You can also
tristate the FPGA device outputs during board level simulation to assist in
debugging simulation. In most cases, GTS is deactivated so that the
outputs are active.
Solution 1:
Alliance 2.1i and later:
Please see (Xilinx Solution 6537) regarding details of glbl.v used to
define the GSR, GR, GTS, and PRLD signals.
In your testfixture, enter the following commands to toggle the global signal,
GSR or set the GSR for the 4000 series, Virtex, and Spartan designs.
reg GSR;
assign glbl.GSR = GSR;
reg GTS;
assign glbl.GTS = GTS;
initial begin
GSR = 1; GTS = 1;
#100 GSR = 0; GTS = 0;
end
To set the GR for the 3000 series, enter the following commands.
reg GR;
assign glbl.GR = GR;
initial begin
GR = 0;
#100 GR = 1;
end
To set the GR for the 5200 series, enter the following commands.
reg GR;
assign glbl.GR = GR;
reg GTS;
assign glbl.GTS = GTS;
initial begin
GR = 1; GTS = 1;
#100 GSR = 0; GTS = 0;
end
To set the PRLD for the 9500 series, enter the following commands.
reg PRLD;
assign glbl.PRLD = PRLD;
initial begin
PRLD = 1;
#100 PRLD = 0;
end
Solution 2:
Alliance 1.4 to 1.5:
Please see (Xilinx Solution 3914) regarding details of the Verilog text
macros used to define the GSR, GR, GTS, and PRLD signals.
In your testfixture, enter the following commands to toggle the global signal,
GSR or set the GSR for the 4000 series, Virtex, and Spartan designs.
reg GSR;
'define GSR_SIGNAL test.GSR
reg GTS;
'define GTS_SIGNAL test.GTS
initial begin
GSR = 1; GTS = 1;
#100 GSR = 0; GTS = 0;
end
To set the GR for the 3000 series, enter the following commands.
reg GR;
'define GR_SIGNAL test.GR
initial begin
GR = 0;
#100 GR = 1;
end
To set the GR for the 5200 series, enter the following commands.
reg GR;
'define GR_SIGNAL test.GR
reg GTS;
'define GTS_SIGNAL test.GTS
initial begin
GR = 1; GTS = 1;
#100 GSR = 0; GTS = 0;
end
To set the PRLD for the 9500 series, enter the following commands.
reg PRLD;
'define PRLD_SIGNAL test.PRLD
initial begin
PRLD = 1;
#100 PRLD = 0;
end
End of Record #5009 - Last Modified: 07/14/99 11:34 |
