Answers Database
2.1i Virtex Map/PAR - Designs combining non-RLOC'd carry chains and macros may fail.
Record #7086
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 2.1i
Problem Title:
2.1i Virtex Map/PAR - Designs combining non-RLOC'd carry chains and macros may fail.
Problem Description:
Map will sometimes merge part (but not all) of a carry chain into a macro.
The result is a partially RLOC'd carry chain that PAR can not correctly
align during placement. Synthesis vendors have been told not to RLOC
Virtex carry chains. When these designs contain instantiated macros,
then there is a good chance that the design will run into placement problems.
It will either fail to place all slices successfully (Xilinx Solution #6999) or at
best the affected carry chains will not be aligned.
The problem of Map merging carry logic into macros will be fixed in a 2.1i
service pack. For related Virtex carry chain issues, also see solution 7243:
(Xilinx Solution #7243)
Solution 1:
This problem is fixed in the latest 2.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/
End of Record #7086 - Last Modified: 10/18/99 10:07 |
