Answers Database 2.1i Virtex Map/PAR - Map and PAR issues related to Virtex Carry chains Record #7243 Product Family: Software Product Line: FPGA Implementation Product Part: map Product Version: 2.1i Problem Title: 2.1i Virtex Map/PAR - Map and PAR issues related to Virtex Carry chains Problem Description: The 2.1 version of PAR can successfully place and align a Virtex carry chain if the carry chain is entirely RLOC'd and contained in a single RPM macro. PAR can also successfully align a carry chain if no part of the carry chain is RLOC'd and consists of independent slice components that are not part of any macro. Problems arise when PAR is forced to deal with a carry chain that is partially RLOC'd where the carry chain consists of multiple macros or a mixture of independent slice components and macros. Failure Modes: 2.1i PAR has a bug where the placer can not successfully place independent slices that are in the same carry chain with a macro. After placement, the router fails with the error:     FATAL_ERROR:Route:xvkrtconn.c:116:1.1.2.4 - UNPLACED COMP ENCOUNTERED Process     will terminate. To resolve this error, please consult the Answers Database     at http://support.xilinx.com A tactical patch is available for the placer that happens to also correct this error. See http://www.xilinx.com/techdocs/6690.htm Using this patch, PAR should be able to place all carry chain slice, but the resulting placement may well contain non-aligned carry chains leading to routing and timing problems. Check for the following warnings during PAR:     WARNING:Place:1592 - RLOC constraints have been applied to a subset of the     slices in the carry chain. Locations of following components not guaranteed to     be in carry chain formation     H60/H56/$I531/I5 The full solution is to recognize the source of the carry chain errors and correct the problem. The following is a summary of map issues that lead to partially RLOC'd carry chains and possible solutions: 1. The most common source of carry chain problems occurs when non-RLOC'd carry elements are "merged" into macros. This can occur either due to "related merging" (carry logic has common inputs with logic already in slice) or "unrelated merging" (carry logic has nothing in common, but is necessary to fit the device). The portion of the carry chain merged into the macro inherits the relative placement of the rest of the slice, resulting in a partially RLOC'd carry chain. A fix is planned for the service pack that will disable all merging of carry logic into macros. For the latest information on this issue, see http://www.xilinx.com/techdocs/7086.htm 2. Carry logic can also be "packed" into a macro which can also lead to a partially RLOC'd carry chain. Packing occurs when the mapper pulls logic into a slice because it either drives or is driven by other logic that is already in the slice. In the case of Virtex carry logic, this will likely only occur when there is a LUT that drives the carry logic from a slice with non-utilized carry circuitry. One way to avoid this problem would be to construct macros with buffered outputs for "at risk" slices, with a KEEP property on the net driving the buffer. The buffer should be pushed forward so that no delay is added to the path. No change is planned to the map software for this issue, because the packing behavior involved is generally necessary. 3. Cases have also been seen where the end of an RLOC'd carry chain has been trimmed as unused, leaving a non-RLOC'd XORCY component at the end of the carry chain. The non- RLOC'd XORCY ends up in a slice component that is separate from the rest of the macro, resulting in a partially RLOC'd carry chain that PAR can not align. The work around is to add an RLOC property to the XORCY instance so that it stays in the RPM. UCF example:     INST "XORCY_NAME" RLOC=RXCY.S0 ; 4. Cases have been seen where customers have chained macros together so that a single carry chain spans multiple macros. PAR can not currently align the macros, so routing and timing issues are likely. The solution is to either LOC the macros to specific sites or reconstruct the logic into a single macro. Solution 1: Long Term Solutions: The first 2.1i service pack will contain a change that addresses the merging issue, solving case 1. Case 2 will remain an issue, but can be avoided by constructing macros to avoid the problem. The first major release (as yet unnamed) following 2.1i will contain a change to the placer algorithm so that partially RLOC'd carry chains can be aligned. This will address cases 3&4, but will not help case 2 if map has packed a carry element into a slice in the middle of a macro. End of Record #7243 - Last Modified: 09/01/99 18:10

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