Answers Database
2.1i TRCE - Paths are reported against the wrong timing constraint.
Record #7340
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Product Version: 2.1i
Problem Title:
2.1i TRCE - Paths are reported against the wrong timing constraint.
Problem Description:
2.1i TRCE shows several paths that are failing timing constraints. Investigation
shows that the failing paths are not being included in the correct timing constraints.
The failing paths show up in the period specification when they should show up in
another from GRP_CHIP to GRP_CHIP constraint (TS_Chip_rate1).
This problem is due to an overflow of an internal table, which consequently
causes identical paths from the period and exception timespec to appear different.
Solution 1:
A fix for this problem is included in the 2.1i Service Pack 1 Update which is
scheduled to become available on September 1.
For more information about the 2.1i Service Pack 1 Update see:
(Xilinx Solution #7317)
End of Record #7340 - Last Modified: 09/02/99 14:24 |
