Answers Database 2.1i SP1 - The 2.1i Service Pack 1 Update is due to become available on September 2. Record #7317 Product Family: Software Product Line: Merged Core Product Part: general Problem Title: 2.1i SP1 - The 2.1i Service Pack 1 Update is due to become available on September 2. Problem Description: The 2.1i Service Pack 1 Update is due to become available on September 2. Solution 1: The Service Pack Update Page is located at: http://www.xilinx.com/support/techsup/sw_updates/ The following issues are addressed by the 2.1i Service Pack 1 Update: NGDBUILD ISSUES     (Xilinx Solution #7307)     Ngdbuild 2.1i: KEEPER is not applied to design IO ports via UCF.     (Xilinx Solution #7071)     2.1i, ngdbuild- ngdbuild ignoring drive strength constraints attached to     nets which drive IOB components (created from constraints editor)     (Xilinx Solution #7351)     2.1i Ngdbuild - TNM_NET propagation thru DLL to no synchronous loads     (two problems). MAP ISSUES     (Xilinx Solution #7325)     2.1i Virtex Map - Map creates bad .pcf constraints from floorplanner     constraints.     (Xilinx Solution #6319)     2.1i 4KX* Floor Planner writes bad constraint leading to error:     ERROR:OldMap:563 - Bel type "PAD" is not supported.     (Xilinx Solution #7279)     2.1i Virtex Map - Map trims inverter when FF pushed into IOB.     (Xilinx Solution #7349)     2.1i Virtex Map - Virtex mapper treats OBUF driving PU, PD, or     KEEPER inconsistently.     (Xilinx Solution #7008)     2.1i Virtex Map - Map may configure a BUFT driven by PWR/GND in a way     that will not work in the hardware.     (Xilinx Solution #6708)     2.1i Virtex Map - ERROR:xvkpu - Unable to obey design constraints...     (Xilinx Solution #7321)     2.1i Virtex Map - The Virtex packer is failing to process the local     output directive properly. PAR ISSUES     (Xilinx Solution #6806)     2.1i Virtex PAR - Placer has been enhanced to use MAXSKEW preference     to assign secondary global clock buffers for external clock nets.     (Xilinx Solution #7086)     2.1i Virtex Map/PAR - Designs combining non-RLOC'd carry chains and macros     may fail.     (Xilinx Solution #6690)     2.1i Virtex PAR - FATAL_ERROR:Place:xvkapanal.c:1860:1.1.2.21.2.1     (Xilinx Solution #6739)     2.1i Virtex PAR - Virtex design is taking too long to route PWR/GND     signals.     (Xilinx Solution #7335)     2.1i SPXL PAR - PAR fails to produce consistent results when running a     cost table twice.     (Xilinx Solution #6953)     2.1i Virtex PAR - Virtex designs with area constraints may run out of     memory during placement.     (Xilinx Solution #7064)     2.1i Virtex PAR - Router terminates with Segmentation fault during     PWR/GND routing.     (Xilinx Solution #7350)     2.1i PAR - PAR does not cleanup low-end results when running turns     engine (ignores -s)     (Xilinx Solution #7345)     2.1i Virtex PAR - Placer leaves source pin of high fanout net unplaced,     leading to router crash.     (Xilinx Solution #7078)     2.1i Virtex PAR - Placer ignores list constraint involving IOB.     (Xilinx Solution #7342)     2.1i SpartanXL PAR - FATAL_ERROR:Route:basrtsanity.c:241:1.1.2.2 -Process     will terminate. TIMING ISSUES     (Xilinx Solution #6964)     2.1i Virtex Timing - There are two known issues where back annotated     Virtex timing under reports delay. (Xilinx Solution #6965) 2.1i 4KE/Spartan Timing - There is a known case where back annotated xc4000e and Spartan delays are under reported.     (Xilinx Solution #6825)     2.1i: Timing Analyzer: TA only produces a summary report of constraints     with no paths for advanced analysis.      (Xilinx Solution #6959)     2.1i: TRCE/NGDBUILD/Timing Analyzer/FPGA Editor: MIN delays & changing     speed grades after implementation does not work     (Xilinx Solution #7340)     2.1i TRCE - Paths are reported against the wrong timing constraint.     (Xilinx Solution #7341)     2.1i Virtex Speed Files - Missing virtex pin-to-pin timing values cause     overly optimistic delays BACK ANNOTATION ISSUES     (Xilinx Solution #7322)     2.1i Virtex Ngdanno - Virtex single and dual port RAM give setup violations     for Physical Sim only.     (Xilinx Solution #7331)     2.1i -Verilog UNSIM and concept models are not using glbl.GSR for     Block RAM     (Xilinx Solution #7336)     2.1i Virtex Ngdanno - Back annotated delay has 3.7ns added to tristate     signal on an IOB.     (Xilinx Solution #6913)     ngdanno: INTERNAL_ERROR:Anno:Ax.c:2094:1.1.2.40.2.4 - Ax::fixConfusedPins()     cannot handle this configuration.   BITGEN ISSUES     (Xilinx Solution #7318)     2.1i 4KX* Bitgen - Some 4000x family devices won't configure via JTAG     (Xilinx Solution #7186)     2.1i Virtex Bitgen - "WARNING:Bitgen:73 - Can't find arc ...." DESIGN MANAGER ISSUES     (Xilinx Solution #6554)     2.1i - Running pld_dsgnmgr through Mentor DM or using the Design     Manager option from Exemplar's P&R tab, can not choose options for     implemention.     (Xilinx Solution #7328)     2.1i Design Manager - DM Overwrite Last Version does not work on     win95/98 & WS     (Xilinx Solution #6660)     Design Manager 2.1i - The server threw an exception     (Xilinx Solution #7343)     2.1i General - Help -> About Project Manager should show whether     service pack revision. JTAGPGMR ISSUES     (Xilinx Solution #7319)     2.1i Virtex Jtagpgmr - Virtex configuration requires shutdown     sequence at beginning     (Xilinx Solution #7324)     2.1i Jtagpgmr on HP - Core dump when running Jtagpgmr from Dsgnmgr.     (Xilinx Solution #6764)     1.5is2 JTAGProgrammer : Cannot generate a SVF file for the 4002xl-pq100     (Xilinx Solution #7049)     2.1i JTAGProgrammer: - Done does not go high when configuring 4010XL CPLD ISSUES     (Xilinx Solution #6683)     HITOP.C.16 - Fitting Report shows VCCIO pins as TIE on XC95288XL-BG256     (Xilinx Solution #7337)     2.1i Hitop - Hitop not fitting DFF--> INV --> OBUF correctly. FLOORPLANNER ISSUES     (Xilinx Solution #6438)     2.1i: Floorplanner: Map file naming is causing problems for the Design     Manager FPGA EDITOR ISSUES     (Xilinx Solution #7334)     2.1i FPGA Editor - Busy cursors are not used on many long processes. COREGEN ISSUES     (Xilinx Solution #6890)     V2.1i COREGEN, Foundation: Coregen may not be able to locate the     Foundation install directory on Windows. SPEED FILES     (Xilinx Solution #7327)     2.1i - New Virtex Speed files are available in 2.1i Service Pack 1.     (Xilinx Solution #7330)     2.1i XC4000XV Speed files - The 2.1i Service Pack 1 Update contains     Preliminary XC4000XV speed data.     (Xilinx Solution #7352)     2.1i SpartanXL Speed Files - Updated speed files are available for -5     Preliminary speed grades. PACKAGE FILES     (Xilinx Solution #7326)     2.1i - SpartanXL - The CS280 packages are missing in M2.1i     (Xilinx Solution #7185)     2.1i package files - The 40150xv BG432 package is incorrect. LIBRARY ISSUES     (Xilinx Solution #6588)     Synopsys FPGA Compiler 1998.08/1999.05: Slew rate specifications on Virtex     IOBs are ignored during synthesis. End of Record #7317 - Last Modified: 11/03/99 10:01

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