Answers Database
2.1i Virtex Speed Files - Missing Virtex pin-to-pin timing values cause overly optimistic delays
Record #7341
Product Family: Software
Product Line: Merged Core
Product Part: speed files
Problem Title:
2.1i Virtex Speed Files - Missing Virtex pin-to-pin timing values cause overly optimistic
delays
Problem Description:
Some FLUT, GLUT and F5MUX slice configurations are missing pin-to-pin delays for F (or G) to X (comb
inatorial), F (or G) to XQ (registered) and CLK to F (G) setup/hold delays. The problem appears to
be in the delay filtering code. The scope of this problem is that we will not report delays (overly
optimistic) in both ngdanno and the static timing analyzer for any of the paths thru the LUTs.
Solution 1:
A fix for this problem is included in the 2.1i Service Pack 1 Update which is
scheduled to become available on September 1.
For more information about the 2.1i Service Pack 1 Update see:
(Xilinx Solution #7317)
End of Record #7341 - Last Modified: 09/02/99 10:08 |
