Answers Database
FPGA Express 3.x: Address lines unconnected when SRL16 components are instantiated (FPGA-CHECK-7)
Record #7812
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 3.2
Problem Title:
FPGA Express 3.x: Address lines unconnected when SRL16 components are instantiated
(FPGA-CHECK-7)
Problem Description:
Urgency: Standard
General Description:
When an SRL16 or SRL16E component is instantiated in a Virtex design in FPGA Express, the
following error will occur for any of the four address pins that are connected:
Warning: The net '/my_srl/addr<0>' has no load. (FPGA-CHECK-7)
If you open the schematic created by FPGA Express and push into the SRL instance, you will
see a large shift register that has no connections for the four address lines. These connections
will be left out of the final EDIF netlist.
Solution 1:
Static length shift registers can be inferred by FPGA Express 3.3. See (Xilinx Solution 5800)
for more information about how this is done.
However, if you need a dynamic length shift register, inference is not possible. The workaround
in this case would be the same as described in (Xilinx Solution 4588); create a schematic
representation of the SRL16 component and instantiate it as a black box.
End of Record #7812 - Last Modified: 11/05/99 12:56 |
