Answers Database
NGD2VER: False setup violation on X_FF instance immediately after time 0
Record #7887
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngd2ver
Product Version: 2.1i
Problem Title:
NGD2VER: False setup violation on X_FF instance immediately after time 0
Problem Description:
Urgency: Standard
General Description:
A setup violation can occur immediately after the start of initialization due to
the settling of initilization values progating longer than the allowed setup of
the FF.
Solution 1:
This is a false setup reported because of time zero startup. It can be safely
ignored because the global reset signal is pulsed to re-initialize the FFs.
To resolve the issue, consider delaying clock until the global reset signal is
pulsed. For example consider the XC4000E case,
`define GSR_PULSE 100
`define CLK_PER 200
initial begin
clk = 0;
// Wait till GSR is finished, then cycle clock
#`GSR_PULSE forever #(`CLK_PER/2) clk = ~clk;
end
reg GSR;
assign glbl.GSR = GSR;
reg GTS;
assign glbl.GTS = GTS;
initial begin
GSR = 1; GTS = 1;
// GSR is finished
#`GSR_PULSE GSR = 0; GTS = 0;
end
Please see (Xilinx Solution 5009) on how to drive the global signals.
End of Record #7887 - Last Modified: 10/21/99 13:48 |
