Answers Database
2.1i COREGEN: Incorrect data written to Virtex Block RAM in VHDL behavioral simulation / model has incorrect timing on address and data lines
Record #7909
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: 2.1i
Problem Title:
2.1i COREGEN: Incorrect data written to Virtex Block RAM in VHDL behavioral simulation /
model has incorrect timing on address and data lines
Problem Description:
Urgency: hot
General Description:
Incorrect data may be written to the CORE Generator 2.1i Single Port and Dual Port
Block RAM during VHDL behavioral simulation due to an error in the behavioral model.
There is a delta delay implied by the declaration of an internal version of the module output
that is not balanced by implied delta delays associated with internal versions of the data
and address signals.
One possible symptom is seen when the rising edge of the clock and the address lines
change at the same time. Under these conditions, the new data appears to be written into
the new address instead of the data that was valid right before the rising edge of the clock.
Solution 1:
Currently the most reliable workaround is to generate a post-NGDBUILD gate level
netlist for the block RAM module as described in (Xilinx Solution #8065), and to use
this in place of the behavioral model.
Solution 2:
You can also use an AFTER statement in your testbench so that
the clock does not transition at the exact same time as data/address
(Ex. address <= address + 1 AFTER 1 ns;).
End of Record #7909 - Last Modified: 02/15/00 12:01 |
