Answers Database
MODELSIM VLOG (MTI): How to compile the XilinxCoreLib (COREGEN) Verilog library?
Record #8066
Product Family: Software
Product Line: Model Technology
Product Part: Modelsim
Product Version: 5.2
Problem Title:
MODELSIM VLOG (MTI): How to compile the XilinxCoreLib (COREGEN) Verilog library?
Problem Description:
Urgency: Standard
General Description:
How to compile the XilinxCoreLib (COREGEN) Verilog library for
ModelSim Vlog?
Solution 1:
1> Extract the Coregen library.
get_models -verilog <destination_directory>
This creates a XilinxCoreLib directory at the specified destination.
Please see (Xilinx Solution 7859) for instructions on extracting this
library.
2> Map and compile the XilinxCoreLib library
vlib xilinxcorelib_ver
vmap xilinxcorelib_ver xilinxcorelib_ver
vlog -work xilinxcorelib_ver <destination_directory>/XilinxCoreLib/*.v
3> Run the simulation, including an additional "-L" option
vsim -L xilinxcore_ver testbench.v design.v
Please see (Xilinx Solution 1078) on how to run simulation.
End of Record #8066 - Last Modified: 12/16/99 14:01 |
