Xilinx Answer #8202 : Virtex-E FPGA Express 3.3: How to instantiate special Virtex-E I/O standards (LVDS, LVPECL)

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Virtex-E FPGA Express 3.3: How to instantiate special Virtex-E I/O standards (LVDS, LVPECL)

Record #8202
Product Family: Software

Product Line: Synopsys

Product Part: FPGA Express

Product Version: 3.2

Problem Title:
Virtex-E FPGA Express 3.3: How to instantiate special Virtex-E I/O standards (LVDS, LVPECL)

Problem Description:
Urgency: Hot

General Description:
FPGA Express 3.3.1 or older contains all the special Virtex I/O Standard buffers. These buffers can be instantiated for any ports and Express will realize they are input or output buffers.

However, FPGA Express 3.3.1 or older does not contain the new Virtex-E I/O buffers, so special techniques must be used when synthesizing.

(Xilinx Solution 8187) contains complete details about using the special Virtex-E I/O buffers.

Solution 1:

If all or most of the ports your design use special Virtex/E I/O standards, one option is to instantiate all of the I/O buffers. Because all the I/O buffers already will then exist in the HDL code, you must not allow FPGA Express to insert I/O buffers. Deselect the "Insert I/O Pads" checkbox Foundation or select the "Do Not Insert I/O Pads" box in FPGA Express.

In these cases, you must do three things:

1. Instantiate all the Virtex, Virtex-E and standard I/O buffers, but NO pads.
2. Include all I/O ports in the top level port declaration.
3. Do NOT allow FPGA Express to insert pads.

Here are some code examples:

Verilog:

module lvds_v_nopads (din, dout_p, dout_n); // NOTE: All ports in the design are listed input din; output dout_p, dout_n; wire data_int, data_n_int;

IBUF_LVDS data0 (.I(din), .O(data_int)); // NOTE: only the buffers are instantiated

OBUF_LVDS data1_p (.I(data_int), .O(dout_p)); assign data_n_int = !data_int; OBUF_LVDS data1_n (.I(data_n_int), .O(dout_n));

endmodule

VHDL:

library IEEE;
use IEEE.std_logic_1164.all;

entity lvds_vhdl_nopads is
   port (din: in STD_LOGIC; -- NOTE: All ports in the design are listed
      dout_p: out STD_LOGIC;
      dout_n: out STD_LOGIC);
end lvds_vhdl_nopads;

architecture lvds_vhdl_nopads_arch of lvds_vhdl_nopads is
signal data_int, data_n_int: STD_LOGIC;

component IBUF_LVDS port
   (I: in STD_LOGIC; O: out STD_LOGIC);
end component;

component OBUF_LVDS port
   (I: in STD_LOGIC; O: out STD_LOGIC);
end component;

begin

data0: IBUF_LVDS port map (I=>din, O=>data_int); -- NOTE: only the buffers are instantiated

data1_p: OBUF_LVDS port map (I=>data_int, O=>dout_p);
data_n_int <= not data_int;
data1_n: OBUF_LVDS port map (I=>data_n_int, O=>dout_n);

end lvds_vhdl_nopads_arch;

Sample UCF for the above HDL code for use with a Virtex 100E-CS144:

NET din LOC = F2; # IO_L26P, in bank0 NET dout_p LOC = A5; # IO_L1P_YY, in bank0 NET dout_n LOC = B5; # IO_L1N_YY, in bank0

Solution 2:

If only a few of the ports in your design use the special VirtexE I/O Standards, you may allow Express to insert pads for all the ports EXCEPT the ones using the Virtex-E standards. Because Express does not know about these buffers, it will place an extra IBUF or OBUF on these ports, which will lead to errors during implementation.

In these cases, you must do three things:

1. Instantiate the Virtex-E buffers AND their pads.
2. Do NOT include these ports in the top level port declaration.
3. Allow FPGA Express to insert pads for all other ports, including any Virtex (non-E)
    instantiated buffers. Check the "Insert I/O Pads" box (Foundation) or uncheck the
    "Do Not Insert I/O Pads" box (FPGA Express).

Here are the code examples from Resolution 1 with extra logic. Ports clk, rst and ce will use the default LVTTL standard, and ports din, dout_p and dout_n use the LVDS standard.

Verilog:

module lvds_v_pads (clk, rst, ce); // NOTE: din, dout_p, and dout_n are not listed input clk, rst, ce; reg data_int, dout_p, dout_n; wire din, din_int, data_n_int;

always @(posedge clk or posedge rst)
begin
    if (rst)
       data_int = 1'b0;
    else if(ce)
       data_int = din_int;
end

IBUF_LVDS data0 (.I(din), .O(din_int));
IPAD data0_pad (.PAD(din)); // NOTE: pads are instantiated along with the VirtexE buffers

OBUF_LVDS data1_p (.I(data_int), .O(dout_p)); OPAD data1_p_pad (.PAD(dout_p)); assign data_n_int = !data_int; OBUF_LVDS data1_n (.I(data_n_int), .O(dout_n)); OPAD data1_n_pad (.PAD(dout_n));

endmodule

VHDL:

library IEEE;
use IEEE.std_logic_1164.all;

entity lvds_vhdl_pads is
   port (clk, rst, ce: in STD_LOGIC); -- NOTE: din, dout_p, and dout_n are not listed
end lvds_vhdl_pads;

architecture lvds_vhdl_pads_arch of lvds_vhdl_pads is
signal din_int, data_int, data_n_int: STD_LOGIC;
signal din, dout_p, dout_n: STD_LOGIC;

component IBUF_LVDS port
   (I: in STD_LOGIC; O: out STD_LOGIC);
end component;

component IPAD port
   (PAD: out STD_LOGIC);
end component;

component OBUF_LVDS port
   (I: in STD_LOGIC; O: out STD_LOGIC);
end component;

component OPAD port
   (PAD: in STD_LOGIC);
end component;

begin

process (clk, rst)
begin
    if rst='1' then
        data_int <= '0';
    elsif (clk'event and clk='1') then
      if (ce='1') then
        data_int <= din_int;
      end if;
    end if;
end process;

data0: IBUF_LVDS port map (I=>din, O=>din_int);
data0_pad: IPAD port map (PAD=>din); -- NOTE: pads are instantiated along with the VirtexE buffers

data1_p: OBUF_LVDS port map (I=>data_int, O=>dout_p);
data1_p_pad: OPAD port map (PAD=>dout_p);
data_n_int <= not data_int;
data1_n: OBUF_LVDS port map (I=>data_n_int, O=>dout_n);
data1_n_pad: OPAD port map (PAD=>dout_n);

end lvds_vhdl_pads_arch;

Sample UCF for the above HDL code for use with a Virtex 100E-CS144:
NET "data0" LOC = F2; # IO_L26P, in bank0 NET "data1_p" LOC = A5; # IO_L1P_YY, in bank0 NET "data1_n" LOC = B5; # IO_L1N_YY, in bank0 NET "clk" LOC = B7; # in bank1 NET "ce" LOC = C8; # in bank1
NET "rst" LOC = D8; # in bank1

Solution 3:

Using IOSTANDARD=LVPECL in the ucf file currently is not supported. Users must
instantiate these buffers explicitly in the HDL codes. If you used LVPECL iostandard in the ucf file, you will receive the error messages documented in (Xilinx Solution 7860).

Using IOSTANDARD=LVDS in the ucf file works fine.

End of Record #8202 - Last Modified: 01/11/00 11:13

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