Answers Database


FPGA Configuration: Configuration has not begun


Record #8213

Product Family: Web

Product Line: support.xilinx.com

Product Part: Configuration Problem Solver

Product Version: 1.0

Problem Title:
FPGA Configuration: Configuration has not begun


Problem Description:
Urgency: Standard

General Description:
This solution record describes conditions to check
if the FPGA is stuck in a state where configuration
has not begun. This information is valid for all Xilinx
devices except for Virtex devices.


Solution 1:

The Mode Pins are set incorrectly.


MODE			  | MODE PINS  |
			  | <M2:M1:M0> |
=======================================================
Slave Serial		  |   111	  | XC4000, XC5200, XC3000
Master Serial		  |   000	       | XC4000, XC5200, XC3000

Master Parallel Up	       |   100		    | XC4000, XC5200, XC3000

Master Parallel Down	     |	 110		  | XC4000, XC5200, XC3000

Synchronous Peripheral	   |   011		| XC4000, XC5200

Asynchronous Peripheral   |   101	       | XC4000, XC5200, XC3000

Express				  |   010	       | XC4000(XLA/XV only), XC5200
MODE			  | MODE PIN  |
=======================================================
Slave Serial		   |	 1	 | Spartan
Master Serial		   |	 0  	 | Spartan
MODE			  | MODE PINS  |
			  | <M1:M0>	  |
=======================================================
Slave Serial		   |	 11	 | Spartan-XL
Master Serial		   |	 10	 | Spartan-XL

Express			   |	 0X	 | Spartan-XL

KEY:
1 : Indicates a logic level high
0 : Indicates a logic level low
X : Indicates a 'don't care'

LOGIC LEVELS:
While all Xilinx devices have internal pullups on the
Mode pins, the strength of these pullups are not tested
or guaranteed. Therefore, you should NEVER leave the
Mode pins floating.

Additionally, when measuring the level of the Mode pins,
you should always measure the voltage levels at the FPGA
package.  This ensures that there was not a connection
error between the driving source and the FPGA Mode pins.
Refer to the chart below for information about valid
logic levels.


DEVICES 	| VOLTAGE  | STANDARD |  DESCRIPTION
			|  (VCC)	 |		   |	
================================================================
XC4000 		|      5	   |	TTL	       | 0 : A logic low in TTL
(A/D/H/L/E/EX)	|	    |		   |	 should be < 0.5 Volts.


Spartan		|	    |		   |	 A pulldown of 4.7KOhm is
XC3000 (A/L)	|	    |		   |	 recommended.
XC5200		|	    |		   | 1 : A logic high in TTL
		|	    |			   | 	 should be > 4.0 Volts.
		|	    |		   |	 A pullup of 3.3KOhm is
		|	    |		   |	 recommended.
=================================================================
XC4000X		|      3.3	  |  LVTTL	   |  0 : A logic low in LVTTL
(XL/XLT/XLA/XV)	|	    |		  | 	  should be < 0.5 Volts.

Spartan-XL	|	    |		  | 	  A pulldown of 4.7KOhm is

		|	    |		  | 	  recommended.

		|	    |		  |  1 : A logic high in LVTLL

		|	    |		  |	  should be > 3.0 Volts.

		|	    |		  | 	  A pullup of 3.3KOhm is

		|	    |			  | 	  recommended.



Solution 2:

The Data pin(s) [DIN or D<7:0>] are not correctly connected
on the board.

Serial Mode:
If you are configuring in a serial mode, probe the DIN Pin
directly at the FPGA package pin. Verify that the configuration
data is reaching the FPGA's pin. Probing a trace or the data
source is not positive proof that the data is reaching the FPGA.

Parallel Mode:
If you are configuring in a parallel mode, although it is unlikely
that all 8 data pins are connected incorrectly, or that only one
or a few of the pins are incorrect without causing a DataFrame
Error (INIT goes low - (Xilinx Answer 8158)),
these conditions could be the result of no configuration data
reaching the FPGA. Probe the Data pins directly at the FPGA
package pins. Verify that the configuration data is reaching the
FPGA's pins. Probing a trace or the data source is not positive
proof that the data is reaching the FPGA.



Solution 3:

The CCLK is not transitioning or is not correctly connected.

Probe the CCLK Pin directly at the FPGA package pin, as well
as the source (if in slave mode) or the destination (if in master
mode). Verify that the clock is indeed transitioning and is well
within the timing specifications for the clock load. If the device
is in a master mode, then try setting the CCLK to SLOW in the
configuration options. If the device is in a slave mode, then try
slowing down the CCLK.



Solution 4:

Boundary Scan has been invoked.

From the moment of power-up Boundary Scan (JTAG)
operations are available within the FPGA. These operations
may be inadvertently invoked by movement on the TCK Pin.
This could result in taking the FPGA out of configuration mode.
Verify that the TMS is high and that the TCK is not moving. If
your application uses a free running clock on TCK then be sure
that TMS is a strong logic `1' and recycle the PROG Pin to restart
configuration.



Solution 5:

This solution applies ONLY to the Express and the Asynchronous
Peripheral (simply called Peripheral in the XC5200) Modes.

The Chip Selects (CS0 and CS1) are not set properly.

Express :
The CS1 is the Chip Select that enables the FPGA for
configuration in the Express Mode. If the CS1 is Low the
FPGA will ignore all CCLK transitions and will not configure.
If this is the lead device in a daisy-chain, or a single device,
attach a pullup resistor to CS1 or make adjustments to
whatever logical device is driving this input to bring it to a
Logic High. If this is a secondary device in a daisy-Chain then
begin trouble shooting why the preceding device did not bring
it's DOUT high which should be driving the CS1.
CS0 is not used for Express mode configuration.

Peripheral / Asynchronous Peripheral :
The Chip Selects CS0 and CS1 must be set to a Logic Low
and a Logic High, respectively, for the FPGA to accept
configuration data in the peripheral mode. Verify the logic
state of these pins.



Solution 6:

For all devices EXCEPT the XC3000 family:
===========================================
The PROG or INIT pin is low :

The PROG pin is an active low input that forces
the FPGA to clear its configuration memory. The
INIT pin is a bidirectional signal before and during
configuration. If this pin is held low, it will delay
configuration. Verify that these signals are not being
continuously driven low on the board, and if they are,
take the appropriate action to release them so that
configuration may begin.

For XC3000 devices:
===========================================
The RESET or PWRDN pin is low :

The RESET pin is an active low input that is a
global reset after configuration, but will restart the
configuration process if active during configuration.
Therefore, configuration will not begin if RESET is low.
The PWRDN pin is an active low input that will power
down the device. PWRDN must be high before and
during configuration. Verify the drivers to these signals,
and ensure that they are at the correct level so that
configuration may begin.



Solution 7:

The FPGA is not properly powered.

Obviously, if an FPGA is not properly powered, it is not going
to function at all. However, this is a possibility that should not
be quickly dismissed. A single mis-connection may be inadvertently
preventing normal operation. Check every VCC, GND, and
configuration related pins (PROG, INIT, DONE (D/P), CCLK, Mode
Pins, etc) for short circuits.




End of Record #8213 - Last Modified: 01/17/00 14:25

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