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This application note illustrates the use of a Xilinx Spartan-II FPGA and an IDT RISC controller in a handheld, consumer electronics platform. Specifically the target application is an MP3 audio player with advanced user interface features. In this application the Spartan device is used to implement the complex system level glue logic required to interface and manage the memory and I/O devices.

The Spartan-II FPGAs provide dedicated blocks of true dual-port RAM, known as Block SelectRAM+ memory. This dedicated memory provides a cost-effective use of resources without sacrificing the existing distributed SelectRAM memory or logic resources. The Block SelectRAM+ memory is fully synchronous for easy timing analysis and is easily initialized at configuration. This additional integration capability makes the Spartan-II family ideal for cost-sensitive applications.

The Spartan-II family provides four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits, which provide zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits that improve and simplify system level design.

This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be changed if the control logic is changed accordingly. Both a common-clock version and an independent-clock version are described.

This application note is offered as complementary text to the configuration section of the Spartan-II data sheet. It is strongly recommended that the Spartan-II data sheet be reviewed prior to reading this note. Spartan-II FPGAs offer a broader range of configuration and readback capabilities than previous generations of Xilinx FPGAs. This note first provides a comparison of how Spartan-II configuration is different from previous Xilinx FPGAs, followed by a complete description of the configuration process and flow. Each of the configuration modes are outlined and discussed in detail, concluding with a complete description of data stream formats, and readback functions and operations.

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature for the Spartan-II family of FPGAs. These curves are graphical representations of IBIS models, which are traditionally used for system and board-level simulation.

This application note describes a simple CPLD-based interface design to configure a Spartan-II device from a parallel EPROM using the Slave Parallel configuration mode.

The Spartan-II FPGA family simplifies high-performance design by offering SelectI/O inputs and outputs. The Spartan-II devices can support 16 different I/O standards with different specifications for current, voltage, I/O buffering, and termination techniques. As a result, the Spartan-II FPGA can be used to integrate discrete translators and directly drive the most advanced backplanes, busses, and memories. This application note describes how to take full advantage of the flexibility of the SelectI/O features and the design considerations to improve and simplify system level design.

The QDR™ SRAM architecture is aimed at the next generation of switches and routers that operate at data rates above 200 MHz, and will serve as the main memory for lookup tables, linked lists, and controller buffer memory. Any new SRAM architecture requires supporting circuitry for both interfacing and control. FPGAs are ideal to implement the control and interface logic, which ties the CPUs to the QDR SRAMs. The Spartan-II FPGA, with its unique and extensive features is an ideal memory controller interface for the QDR SRAM.

This paper presents an overview of Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) solutions using Xilinx Spartan-II components with IP core technology from Xilinx AllianceCORE partner Xentec, Inc.

The 8051 microcontroller IP in a Spartan-II FPGA shows the advantages of using programmable logic devices (PLDs) as 8-bit microcontrollers. The Xilinx Spartan-II 8-bit microcontroller solution is ideal for applications in which cost and integration within a system is critical. With the flexibility to allow integration of other IP on the FPGA fabric, the Spartan-II family presents an ideal embedded solution. This positions the Spartan-II family uniquely in being able to compete with stand-alone ASSPs. This white paper presents a brief history, the market space for 8-bit microcontrollers, the Spartan-II 8-bit microcontroller solutions, 8051 IP solutions, applications and the Spartan-II FPGA advantage.

Through the value proposition of the DES/TDES IP in a Spartan-II FPGA, the programmable ASSP message is further confirmed. There is an immense value in integrating critical IP solutions like Discrete Cosine Transform/Inverse DCT and DES within a Xilinx FPGA to enhance performance and security in communication applications. A FPGA-based DES/TDES solution provides the necessary scalability and flexibility to handle all these applications and allows for tracking of new standards.

Highly adaptable and design-flexible, FPGAs provide optimal device utilization through conservation of board space and system power - important advantages not available with many stand-alone DSP chips. Xilinx Spartan-II FPGAs provide digital designers with a potentially unlimited array of highly reconfigurable solutions. When the design demands more than 100 MIPS, when time-to-market is critical, or when design adaptability is crucial, Spartan-II FPGAs are the best solution. The most common digital building blocks, like serial peripherals, DMA controllers, PCI controllers, and synthesizable processors, are all readily realizable using a Spartan-II device. In fact, all the most basic operations performed by analog or digital electronic devices - filtering, amplification, modulation, storage, and computation - can be implemented with Spartan-II FPGAs.

Gives an overview of digital modem technologies and how Xilinx high volume programmable devices can be used to implement complex system level glue in digital modem designs. The Xilinx device families targeted at these high volume applications include XC9500 CPLDs and Spartan FPGAs.

This document starts with an overview of the various digital modem technologies and the factors driving their deployment. We next examine the major functional blocks of a digital modem and give an overview of the ASSPs that are used in each functional block. We then illustrate the system level glue functions that are needed in several different digital modem configurations.

While this document focuses on applications of these devices in digital modems, the examples discussed illustrate many of the issues found in other designs; specifically, how to cost effectively interface complex ASSPs with incompatible interfaces. The ASIC vendors have abandoned the traditional solution for this class of problems, the small ASIC, as they moved towards the system-on-chip market. Fortunately for system designers, new classes of low cost PLDs such as the Spartan family have filled this void with devices that replace low density ASICs and retain the time-to-market advantages of FPGAs.

This white paper gives an overview of ISDN modem technologies and how Xilinx high volume programmable devices can be used to implement complex system level glue in ISDN modem designs. The Xilinx device families targeted at these high volume applications include XC9500 CPLDs and Spartan FPGAs.

This document starts with an overview of ISDN technology and how ISDN modems are used. We next examine the major functional blocks of an ISDN modem and give an overview of the ASSPs that implement ISDN functions. We then illustrate the system level glue functions that are needed by way of a design example.

A programmable ASSP solution for transmitting high-bandwidth data over multiple T1 or E1 lines.

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Spartan-II Product Information