Good Hardware from Good Software

Forge technology not only generates synthesizable register transfer level (RTL) specifications from high level language software; it also provides the opportunity to explore a different way of thinking about hardware design.

Other approaches to the hardware design productivity challenge have been hardware-centric: identify the RTL constructs that designers typically use and devise a way to capture those constructs in software.  The problem is that RTL semantics are based upon the notions of data flow and control, while software languages have evolved within the framework of CPU-based Von Neumann (fetch-execute-store) architectures.  The only way to get explicit hardware constructs into procedural languages like C, C++, or even Java is to force them in by extending the source language with specialized library calls or, even worse, with proprietary and non-portable language features.  The results are, not surprisingly, unimpressive with respect to both productivity and design quality.

At Xilinx we recognized that in order to make any significant advances in the productivity and quality of hardware design, we needed to set designers free of RTL constraints altogether and allow them to think in terms of algorithms and system concepts.  That is why our approach has been very software-centric: take the algorithmic semantics of software and find a way to translate them into functionally equivalent and efficient hardware.  That has been the focus of our basic research, which has come to fruition in the Forge.

Too Good to be True?

When we began, there was little doubt that software could be translated into an equivalent logic design.  For instance, one could simply generate a generic (and inefficient) microsequencer and associated firmware.  But our approach focused on extracting a minimized representation of the software algorithm and carefully reconstructing it in terms of data and control flow. The quality of the Forge-generated RTL surprised even us.

Both internally generated examples and challenge problems from cooperating vendors such as Sun Microelectronics and TranSwitch were run through the Forge.  In virtually all cases, the quality metrics of the Forge results met or exceeded those of the equivalent hand-coded RTL.  And as expected, use of the Forge increased productivity by an order of magnitude.

Revolutionary Concept, Open Implementation

We understand that modifying a design group's existing tool chain can be very disruptive.  That is why the Forge was designed from the beginning to support gradual insertion into a hardware design process.  RTL can be generated for an entire design or for a single module and is fully synthesizable with existing tools.

While implemented in Java, the Forge is a general purpose software-to-RTL compiler.  The Forge does not operate upon Java source code, but instead processes Java Virtual Machine bytecode language, which is a portable, implementation-independent assembly language.  Having this bytecode language as our front end allows us to process any source language that can be compiled into that bytecode language, including C and C++.  This means that the Forge has an open front-end that is independent of the source language used.  And that means more choices, smaller learning curve, and greater compatibility for hardware designers.