ARM7TDMI Block Diagram

  • Von Neumann Architecture

  • 32-bit Data Bus

  • 32-bit Address Bus

  • 3-stage pipeline
    • fetch, decode, execute

  • 37 32-bit registers

  • 32-bit ARM instruction set

  • 16-bit THUMB instruction set

  • 32x8 Multiplier Barrel Shifter

The processor architecture is Von Neumann load/store architectury which is characterized by a single data and address bus for instructions and data.