XC9500 CPLD Applications

to view the PDF files below.

Application Notes

XAPP No.	Title	Ver.	Date	Size
XAPP110	XC9500 CPLD Power Sequencing	1.0	1/98	30 kB
XAPP109	Hints, Tips and Tricks for using XABEL with Xilinx M1.4 Design and Implementation Tools	1.0	2/98	90 kB
XAPP105	A CPLD VHDL Introduction	1.0	1/98	60 kB
XAPP104	A Quick JTAG ISP Checklist	1.0	1/98	10 kB
XAPP103	The Tagalyzer - A JTAG Boundary Scan Debug Tool	1.0	1/98	130 kB
XAPP102	XC9500 Remote Field Upgrade Associated PC and UNIX design files	1.0	1/98	80 kB
XAPP079	4Mbit Virtual SPROM Associated ABEL Design and JEDEC Programming File	1.2	9/97	53 kB
XAPP078	XC9536 ISP Demo Board Johnson Shift Counter VHDL Code Johnson Shift Counter ABEL Code VHDL Design Files	1.0	4/97	41 kB
XAPP077	Metastability Considerations	1.0	1/97	23 kB
XAPP076	Embedded Instrumentation Using XC9500 CPLDs	1.0	1/97	39 kB
XAPP075	Using ABEL with Xilinx CPLDs	1.0	1/97	53 kB
XAPP074	Pin Preassigning with XC9500 CPLDs	1.3	6/98	50 kB
XAPP073	Designing with XC9500 CPLDs	1.3	1/98	70 kB
XAPP072	XC9500 Design Optimization	1.0	1/97	42 kB
XAPP071	Using the XC9500 Timing Model	1.0	1/97	47 kB
XAPP070	Using In-System Programmability in Boundary-Scan Systems	1.1	7/97	42 kB
XAPP069	Using the XC9500 JTAG Boundary-Scan Interface	2.0	2/98	122 kB
XAPP068	In-System Programming Times	1.2	4/98	13 kB
XAPP067	Using Serial Vector Format Files to Program XC9500 Devices In-System on Automatic Test Equipment and Third Party Tools	1.1	7/97	40 kB
XAPP058	XC9500 In-System Programming Using an Embedded Microcontroller Associated files are available for PC, SunOS, Solaris, and HP (files updated 3/98)	1.2	1/98	130 kB

XBRF No.	Title	Ver.	Date	Size
XBRF010	FastFLASH : A New Electrically Erasable CPLD Technology	1.0	1/97	44 kB
XBRF009	XC9500 Pin-Locking Capability and Benchmarks	1.3	1/97	47 kB
XBRF018	Converting XC7200/XC7300 Designs to XC9500 Solutions	1.0	7/97	21 kB

Title	Ver.	Date	Size
Programming Xilinx XC9500 CPLDs on HP 3070 Testers	1.3	12/97	60 kB
Associated files are available for PC, HP, Solaris, and SunOS	1.43	6/98
Programming Xilinx XC9500 CPLDs on GenRad Testers EZTag Version	1.1	3/98	50 kB
Associated files are available for PC and SCO UNIX	1.4	2/98
Programming Xilinx XC9500 on a Teradyne Z1800 with DFP - EZTag Version	1.0	6/97	59 kB
Associated files are available for PC	2.30.014	6/97
Serial Vector Format (SVF) and JEDEC files for verifying blank XC9500 devices	1.0	5/98	206 kB
Using Serial Vector Format Files to Program XC9500 Devices In-System on Automatic Test Equipment and Third Party Tools (XAPP067)	1.1	7/97	40 kB

Title	Issue
Concurrent ISP Operations in JTAG Programmer v1.4	Q2 '98
Q&A: JTAG Programmer	Q2 '98
Q2'98 Component Availability Chart	Q2 '98
Ericsson Telecom - Using XC9500 CPLDs for High-Performance Telecommunications Equipment	Q1 '98
Using XC9500 JTAG and ISP in Manufacturing	Q1 '98
Designing With XC9500 CPLD Family User-Programmable Grounds	Q1 '98