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ASIC Features
ASIC Pricing Xilinx can offer ASIC production pricing because the Spartan series has substantially reduced the die size and manufacturing costs. Cost targets were realized by using an advanced fabrication process and streamlining the FPGA features. Spartan series die has been decreased to limits imposed by the I/O pads and, as a result, has reached die size parity with many gate arrays. The Spartan FPGA and a mask ASIC with the same number of pins are equivalent in both size and cost. Spartan FPGAs offer volume production prices as low as $2.49 for Spartan-XL devices (5,000 system gates). Major ASIC Vendors Exit the Gate Array Business The mask ASIC is actually penalized when migrating to the advanced deep sub-micron technologies at 0.35 mm & beyond. The penalty occurs because the transistors in deep sub-micron devices have shrunk much faster than metal lines. The result is that interconnect delay now dominates gate delay. Minimizing interconnect delay requires adding metal mask layers to create more routing resources. Each photo mask for the 0.35-mm process, unfortunately, costs the ASIC supplier from $12,000-$15,000, as well as extends the prototype fab time. Since most ASICs today are fabricated with four or five custom metal layers, a $60,000-$75,000 cost for photo masks for each different customer design easily results in more than $100,000 in Non-Recurring Engineering (NRE) charges to the customer! The Spartan FPGA does not incur the same cost penalties of ASICs because each photo mask is created only once over the lifetime of the programmable device and serves hundreds of different customers. A deep sub-micron gate array loses much of its traditional value when NREs are increased to more than $100,000 and prototype time is extended. This is a primary reason leading gate array vendors, such as LSI Logic and Motorola, have exited the gate array business to focus on the high complexity Standard Cell market. Total Cost Management Program Spartan FPGAs also apply an aggressive Total Cost Management Program to hold product costs low. For example, the Xilinx Spartan series has
The graph below plots the Spartan series parts according to system gates and number of I/O. As indicated, Spartan FPGAs are most cost competitive in the low density/high I/O (lower right) segment. The graph may be used as a reliable indicator to determine where the Spartan FPGAs can be most competitive with the ASIC in mass production. In short, when the Spartan FPGAs have the same number of I/Os as the ASIC and meet the density needs of your design, the FPGA will clearly be a better choice. By choosing Spartan devices you receive the time-to-production and reprogrammability advantages of FPGAs at ASIC prices.
Immediate Production A fast ramp to full production is a primary advantage of these ASIC Replacement FPGAs. Spartan series deliveries are off the shelf from the Xilinx factory or from the inventory of our distribution partners, while typical ASIC lead times run from 8-16 weeks. Immediate Spartan FPGA production enables fast stocking of your sales channels and the rapid penetration of your customer base. Spartan FPGAs help you avoid the delays resulting from the long ASIC lead times that may substantially decrease revenues and profits throughout the life of the product. A well known McKinsey study found that a six month delay costs one third of the profits over the lifetime of the product. No FPGA Conversions for Spartan Series Users The ASIC prices of Spartan series devices eliminate the need for low-density FPGA conversions to mask gate arrays. The Spartan FPGA user speeds time-to-production, minimizes development/NRE costs, and avoids unnecessary re-design risks by foregoing an FPGA-to-ASIC redesign.
Converging HDL Design Methodologies ASIC and FPGA Converging Design Approach Today, the design methodologies have converged to the extent both ASIC and Xilinx FPGA design flows support behavioral simulation, extensive use of cores, RTL synthesis, timing and functional simulation, static timing analysis, floorplanning, etc. Xilinx has added other widely used ASIC-like tools such as minimum delay timing reports, more comprehensive static timing, team approach modular design and much more.
Xilinx HDL Training for Programmable Logic Xilinx FAEs are available to work with ASIC designers to ease the learning curve of programmable designs. In addition, Xilinx offers formal instruction in HDL design through Xilinx training courses. Comparing ASIC and Spartan FPGA HDL Design Flows  More Information on ASIC Replacement FPGAs
ISD Magazine article: The
New ASIC Replacement FPGAs |
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