Spartan-II Application Notes

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Title Size Design

XAPP134: Synthesizable High Performance SDRAM Controller 100 KB
VHDL, PC
VHDL, UNIX
Verilog, PC
Verilog, UNIX

Synchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The Spartan-II FPGA family has many features, such as the SelectI/O interface and the Delay-Locked Loop (DLL), that make it easy to interface to high speed synchronous Drams This application note describes the design and implementation of a synthesizable, parameterizable, flexible, automatically placed and routed, synchronous DRAM controller.

XAPP136: Synthesizable 200 MHz ZBT SRAM Interface 40 KB PC
UNIX

Spartan-II FPGAs provide access to a variety of on-chip and off-chip RAM resources. In addition to the on-chip SelectRAM and Block SelectRAM+ memory, a Spartan-II design can interface to Megabytes of external high-speed SRAM and DRAM. The combination of high speed SelectI/O and on-chip Clock Delay-Locked Loop enables the interface to operate at maximum RAM speeds. A Spartan-II interface to ZBT (Zero Bus Turnaround) SRAM provides interleaved Read/Write without wasteful turnaround cycles.

XAPP169: MP3 NG: A Next Generation Consumer Platform 360 KB -

This application note illustrates the use of a Xilinx Spartan-II FPGA and an IDT RC32364 RISC controller in a handheld, consumer electronics platform. Specifically the target application is an MP3 audio player with advanced user interface features. In this application the Spartan device is used to implement the complex system level glue logic required to interface and manage the memory and I/O devices.

XAPP173: Using Block SelectRAM+ Memory in Spartan-II FPGAs 140 KB -

The Spartan-II FPGAs provide dedicated blocks of true dual-port RAM, known as Block SelectRAM+ memory. This dedicated memory provides a cost-effective use of resources without sacrificing the existing distributed SelectRAM memory or logic resources. The Block SelectRAM+ memory is fully synchronous for easy timing analysis and is easily initialized at configuration. This additional integration capability makes the Spartan-II family ideal for cost-sensitive applications.

XAPP174: Using Delay-Locked Loops in Spartan-II FPGAs 120 KB PC
UNIX

The Spartan-II family provides four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits, which provide zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits that improve and simplify system level design.

XAPP175: High Speed FIFOs In Spartan-II FPGAs 50 KB PC
UNIX

This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be changed if the control logic is changed accordingly. Both a common-clock version and an independent-clock version are described.

XAPP176: Spartan-II FPGA Family Configuration and Readback 400 KB -

This application note is offered as complementary text to the configuration section of the Spartan-II data sheet. It is strongly recommended that the Spartan-II Data Sheet be reviewed prior to reading this note. Spartan-II FPGAs offer a broader range of configuration and readback capabilities than previous generations of Xilinx FPGAs. This note first provides a comparison of how Spartan-II configuration is different from previous Xilinx FPGAs, followed by a complete description of the configuration process and flow. Each of the configuration modes are outlined and discussed in detail, concluding with a complete description of data stream formats, and readback functions and operations.

XAPP177: Spartan-Family I/V Curves for Various Output Options 30 KB IBIS

These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature for the Spartan-II family of FPGAs. These curves are graphical representations of IBIS models, which are traditionally used for system and board-level simulation.

XAPP178: Configuring Spartan-II FPGAs from Parallel EPROMs 100 KB -

This application note describes a simple CPLD-based interface design to configure a Spartan-II device from a parallel EPROM using the Slave Parallel configuration mode.

XAPP179: Using SelectI/O Interfaces in Spartan-II FPGAs 300 KB -

The Spartan-II FPGA family simplifies high-performance design by offering SelectI/O inputs and outputs. The Spartan-II devices can support 16 different I/O standards with different specifications for current, voltage, I/O buffering, and termination techniques. As a result, the Spartan-II FPGA can be used to integrate discrete translators and directly drive the most advanced backplanes, busses, and memories. This application note describes how to take full advantage of the flexibility of the SelectI/O features and the design considerations to improve and simplify system level design.

XAPP200: Synthesizable 1.6 Gbytes/s DDR SDRAM Controller 100 KB
64-bit, PC
64-bit, UNIX
16-bit, PC
16-bit, UNIX

The DLLs and the SelectI/O features in the Spartan-II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. This application note describes the reference controller design for a 64-bit DDR SDRAM. At a clock rate of 100 MHz, and data changing at both clock edges, a peak bandwidth of 1.6 Gbytes/s is obtained. The reference design is synthesizable and achieves 100-MHz performance with automatic place and route tools.

XAPP211: Pseudo-Random Noise Generators Using the SRL Macro 60 KB
PC
UNIX

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) can be configured as a 16-bit shift register (SRL16 macro). Hence, Xilinx devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop only PLD structures. For example, a 16-stage LFSR can be realized in just one LUT.

WP103: Xilinx High Volume Programmable Logic Applications in Internet Audio Players 120 KB -

This paper provides an overview of Internet audio technologies and how Xilinx high-volume programmable devices can be used to overcome some of the significant challenges facing the designers of portable players. The Xilinx device families targeted at these high-volume applications include CoolRunner CPLDs and Spartan FPGAs. While this document focuses on applications of these devices in portable audio player applications, the examples discussed illustrate many of the issues found in other portable consumer electronics applications.

WP106: The Spartan-II Family – The Complete Package (ASSP Replacement) 340 KB -

The Spartan-II family, combined with a vast soft IP portfolio, is the first programmable logic solution to effectively penetrate the ASSP marketplace. Spartan-II FPGAs offer more than 100,000 system gates at under $10 and are the most cost-effective PLD solution ever offered. They build on the capabilities of the very successful Virtex family and supports all the associated features, including SelectI/O, block RAM, distributed RAM, DLLs, and clock speeds up to 200 MHz. Spartan-II FPGAs extend the Spartan series focus in competing against ASICs and are uniquely poised to penetrate the ASSP marketplace.

WP107: Inverse Multiplexing for ATM (IMA) Solutions with Spartan-II FPGAs 80 KB -

The ATM IMA-8 solution from Applied Telecom ported on the XC2S150 highlights the concept of a programmable ASSP. Applied Telecom is a member of the Xilinx AllianceCORE program and brings a wealth of expertise in ATM, SONET, telecommunications, and networking applications. The IMA-8 core, developed, sold, and supported by Applied Telecom, targets network access systems such as adapters, multiplexers, and switches. The IMA-8 core is available immediately for use in Spartan-II FPGAs. An evaluation board and the DRV-IMA software are also available now.

WP109: HDLC Controller Solutions with Spartan-II FPGAs 140 KB -

Using the Spartan-II family in combination with a soft IP to effectively penetrate the HDLC Controller market in place of the traditional ASSP. The Spartan-II product family brings the density, extensive features, high performance and low cost which makes it the preferred HDLC Controller solution within different data networking applications. A Spartan-II FPGA based HDLC Controller solution with efficient partitioning of hardware and software functions provides the necessary scalability and flexibility to make it the first PLD to effectively penetrate the ASSP marketplace.

WP110: Reed-Solomon Solutions with Spartan-II FPGAs 150 KB -

Xilinx recently announced availability of LogiCORE Reed-Solomon products under a joint development program and OEM agreement with Integrated Silicon Systems, Ltd. (ISS). The new LogiCORE Reed-Solomon cores are based on ISS' already proven and widely used HDL-based cores. Xilinx has optimized the implementation to its FPGA families and incorporated its unique Smart-IP Technology, which uses the relational placement constraint capabilities of Xilinx development software tools to leverage the distributed memory and segmented routing of the FPGAs. As a result, the user can easily customize the Reed-Solomon core and always achieve a predictable, highly-optimized implementation with highest possible performance, unaffected by device size and surrounding user logic. Xilinx also provides Reed-Solomon IP through AllianceCORE partners Memec Design Services (MDS) and ISS. The Reed-Solomon solutions from Xilinx on a Spartan-II device are good examples highlighting the concept of a programmable ASSP.

White Paper - Xilinx at Work in Printers

This white paper focuses on the market size for the various printer technologies, both by performance and geographic region. It then discusses the basics of the technologies, to give a view of their capabilities, limitations and future directions. A functional block diagram is provided which shows the presence of several important application specific standard products (ASSP) providers. We'll focus on exactly where Xilinx XC9500XL CPLDs and Spartan-XL and Spartan-II FPGAs play a vital role in this important market, then take a look into the future direction it is headed with Internet influence and the new photographic quality printers and multi-function peripherals. Finally, a set of additional resources is provided for further study.

Title	Size	Design
XAPP134: Synthesizable High Performance SDRAM Controller	100 KB	VHDL, PC VHDL, UNIX Verilog, PC Verilog, UNIX
Synchronous DRAMs are available in speed grades above 100 MHz using LVTTL I/Os. The Spartan-II FPGA family has many features, such as the SelectI/O interface and the Delay-Locked Loop (DLL), that make it easy to interface to high speed synchronous Drams This application note describes the design and implementation of a synthesizable, parameterizable, flexible, automatically placed and routed, synchronous DRAM controller.
XAPP136: Synthesizable 200 MHz ZBT SRAM Interface	40 KB	PC UNIX
Spartan-II FPGAs provide access to a variety of on-chip and off-chip RAM resources. In addition to the on-chip SelectRAM and Block SelectRAM+ memory, a Spartan-II design can interface to Megabytes of external high-speed SRAM and DRAM. The combination of high speed SelectI/O and on-chip Clock Delay-Locked Loop enables the interface to operate at maximum RAM speeds. A Spartan-II interface to ZBT (Zero Bus Turnaround) SRAM provides interleaved Read/Write without wasteful turnaround cycles.
XAPP169: MP3 NG: A Next Generation Consumer Platform	360 KB	-
This application note illustrates the use of a Xilinx Spartan-II FPGA and an IDT RC32364 RISC controller in a handheld, consumer electronics platform. Specifically the target application is an MP3 audio player with advanced user interface features. In this application the Spartan device is used to implement the complex system level glue logic required to interface and manage the memory and I/O devices.
XAPP173: Using Block SelectRAM+ Memory in Spartan-II FPGAs	140 KB	-
The Spartan-II FPGAs provide dedicated blocks of true dual-port RAM, known as Block SelectRAM+ memory. This dedicated memory provides a cost-effective use of resources without sacrificing the existing distributed SelectRAM memory or logic resources. The Block SelectRAM+ memory is fully synchronous for easy timing analysis and is easily initialized at configuration. This additional integration capability makes the Spartan-II family ideal for cost-sensitive applications.
XAPP174: Using Delay-Locked Loops in Spartan-II FPGAs	120 KB	PC UNIX
The Spartan-II family provides four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits, which provide zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits that improve and simplify system level design.
XAPP175: High Speed FIFOs In Spartan-II FPGAs	50 KB	PC UNIX
This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be changed if the control logic is changed accordingly. Both a common-clock version and an independent-clock version are described.
XAPP176: Spartan-II FPGA Family Configuration and Readback	400 KB	-
This application note is offered as complementary text to the configuration section of the Spartan-II data sheet. It is strongly recommended that the Spartan-II Data Sheet be reviewed prior to reading this note. Spartan-II FPGAs offer a broader range of configuration and readback capabilities than previous generations of Xilinx FPGAs. This note first provides a comparison of how Spartan-II configuration is different from previous Xilinx FPGAs, followed by a complete description of the configuration process and flow. Each of the configuration modes are outlined and discussed in detail, concluding with a complete description of data stream formats, and readback functions and operations.
XAPP177: Spartan-Family I/V Curves for Various Output Options	30 KB	IBIS
These typical curves describe the output sink and source current for average processing, nominal supply voltage and room temperature for the Spartan-II family of FPGAs. These curves are graphical representations of IBIS models, which are traditionally used for system and board-level simulation.
XAPP178: Configuring Spartan-II FPGAs from Parallel EPROMs	100 KB	-
This application note describes a simple CPLD-based interface design to configure a Spartan-II device from a parallel EPROM using the Slave Parallel configuration mode.
XAPP179: Using SelectI/O Interfaces in Spartan-II FPGAs	300 KB	-
The Spartan-II FPGA family simplifies high-performance design by offering SelectI/O inputs and outputs. The Spartan-II devices can support 16 different I/O standards with different specifications for current, voltage, I/O buffering, and termination techniques. As a result, the Spartan-II FPGA can be used to integrate discrete translators and directly drive the most advanced backplanes, busses, and memories. This application note describes how to take full advantage of the flexibility of the SelectI/O features and the design considerations to improve and simplify system level design.
XAPP200: Synthesizable 1.6 Gbytes/s DDR SDRAM Controller	100 KB	64-bit, PC 64-bit, UNIX 16-bit, PC 16-bit, UNIX
The DLLs and the SelectI/O features in the Spartan-II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. This application note describes the reference controller design for a 64-bit DDR SDRAM. At a clock rate of 100 MHz, and data changing at both clock edges, a peak bandwidth of 1.6 Gbytes/s is obtained. The reference design is synthesizable and achieves 100-MHz performance with automatic place and route tools.
XAPP211: Pseudo-Random Noise Generators Using the SRL Macro	60 KB	PC UNIX
Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) can be configured as a 16-bit shift register (SRL16 macro). Hence, Xilinx devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop only PLD structures. For example, a 16-stage LFSR can be realized in just one LUT.
WP103: Xilinx High Volume Programmable Logic Applications in Internet Audio Players	120 KB	-
This paper provides an overview of Internet audio technologies and how Xilinx high-volume programmable devices can be used to overcome some of the significant challenges facing the designers of portable players. The Xilinx device families targeted at these high-volume applications include CoolRunner CPLDs and Spartan FPGAs. While this document focuses on applications of these devices in portable audio player applications, the examples discussed illustrate many of the issues found in other portable consumer electronics applications.
WP106: The Spartan-II Family – The Complete Package (ASSP Replacement)	340 KB	-
The Spartan-II family, combined with a vast soft IP portfolio, is the first programmable logic solution to effectively penetrate the ASSP marketplace. Spartan-II FPGAs offer more than 100,000 system gates at under $10 and are the most cost-effective PLD solution ever offered. They build on the capabilities of the very successful Virtex family and supports all the associated features, including SelectI/O, block RAM, distributed RAM, DLLs, and clock speeds up to 200 MHz. Spartan-II FPGAs extend the Spartan series focus in competing against ASICs and are uniquely poised to penetrate the ASSP marketplace.
WP107: Inverse Multiplexing for ATM (IMA) Solutions with Spartan-II FPGAs	80 KB	-
The ATM IMA-8 solution from Applied Telecom ported on the XC2S150 highlights the concept of a programmable ASSP. Applied Telecom is a member of the Xilinx AllianceCORE program and brings a wealth of expertise in ATM, SONET, telecommunications, and networking applications. The IMA-8 core, developed, sold, and supported by Applied Telecom, targets network access systems such as adapters, multiplexers, and switches. The IMA-8 core is available immediately for use in Spartan-II FPGAs. An evaluation board and the DRV-IMA software are also available now.
WP109: HDLC Controller Solutions with Spartan-II FPGAs	140 KB	-
Using the Spartan-II family in combination with a soft IP to effectively penetrate the HDLC Controller market in place of the traditional ASSP. The Spartan-II product family brings the density, extensive features, high performance and low cost which makes it the preferred HDLC Controller solution within different data networking applications. A Spartan-II FPGA based HDLC Controller solution with efficient partitioning of hardware and software functions provides the necessary scalability and flexibility to make it the first PLD to effectively penetrate the ASSP marketplace.
WP110: Reed-Solomon Solutions with Spartan-II FPGAs	150 KB	-
Xilinx recently announced availability of LogiCORE Reed-Solomon products under a joint development program and OEM agreement with Integrated Silicon Systems, Ltd. (ISS). The new LogiCORE Reed-Solomon cores are based on ISS' already proven and widely used HDL-based cores. Xilinx has optimized the implementation to its FPGA families and incorporated its unique Smart-IP Technology, which uses the relational placement constraint capabilities of Xilinx development software tools to leverage the distributed memory and segmented routing of the FPGAs. As a result, the user can easily customize the Reed-Solomon core and always achieve a predictable, highly-optimized implementation with highest possible performance, unaffected by device size and surrounding user logic. Xilinx also provides Reed-Solomon IP through AllianceCORE partners Memec Design Services (MDS) and ISS. The Reed-Solomon solutions from Xilinx on a Spartan-II device are good examples highlighting the concept of a programmable ASSP.
White Paper - Xilinx at Work in Printers
This white paper focuses on the market size for the various printer technologies, both by performance and geographic region. It then discusses the basics of the technologies, to give a view of their capabilities, limitations and future directions. A functional block diagram is provided which shows the presence of several important application specific standard products (ASSP) providers. We'll focus on exactly where Xilinx XC9500XL CPLDs and Spartan-XL and Spartan-II FPGAs play a vital role in this important market, then take a look into the future direction it is headed with Internet influence and the new photographic quality printers and multi-function peripherals. Finally, a set of additional resources is provided for further study.