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Xilinx DSP Overview - Contents Other Links
[] The High Performance DSP Challenge [] Keynote Speech at ICASSP99 now on-line
[] Parallel Processing [] Xilinx DSP Press Release
[] High Performance and Lower Cost [] DSP Brochure
[] Spartan Lowers The Cost [] DSP Documents
[] Design with DSP System-level Tools [] DSP Development Partners
[] Xilinx CORE Generator & Smart-IP Technology [] Xilinx CORE Generator
[] Add a Xilinx FPGA, Not Multiple Processors [] CORE Solutions - What's New
[] Availability [] IP Center


Xilinx DSP Overview

The High Performance DSP Challenge

Applications such as data communications and image processing require extensive processing power, but when the fastest DSP processor is not fast enough, the only alternatives have been to add multiple DSP processors or to use custom gate arrays.

High Performance DSP image


Multiple DSP processor solutions are expensive, require many components, and consume too much power. The development and debugging of multi-processor software delays new product introduction, and the solution does not always provide the performance needed to differentiate products.

Custom gate array solutions deliver the performance but sacrifice flexibility and require a large engineering investment with no chance to recover from mistakes. The cost, risk, and development time are prohibitive in many applications.

FPGAs Address the High Performance DSP Challenge

FPGAs are a better solution for implementing computationally intensive algorithms. FPGAs offer the best of both worlds, the flexibility of a programmable solution and the performance of a custom solution.

Parallel Processing

Different from conventional data processing, DSP operations lend themselves to highly pipelined parallel execution and the Xilinx XC4000 architecture with thousands of look-up-tables and flip-flops is the ideal platform for this. Compared to general-purpose DSP processors, Xilinx FPGAs achieve identical results much faster and at a lower cost. Compared to dedicated ASIC solutions, Xilinx FPGAs offer faster time-to-market and less risk. And now Xilinx has software tools to help automate this new way of implementing familiar DSP algorithms.

Design with DSP Cores

Most of the standard DSP functions have been implemented in a library of parametizable DSP cores that are delivered through the CORE Generator. Functions include multipliers, square root, FIR filters, comb filters, integrators, sine/cosine tables, and, DFT, FFT and DCT coordinate transforms. Xilinx DSP consists of:

  • SystemLINX to DSP System-level tools
  • Xilinx CORE Generator
  • Xilinx DSP LogiCOREs
  • Xilinx FPGA devices - Spartan and XC4000
  • AllianceCORE DSP prototyping boards
Xilinx DSP the CORE of a Great Idea

High Performance and Lower Cost

Performance gains of more than one order of magnitude are available with Xilinx DSP at a small fraction of the cost compared to multiple processor solutions. The Xilinx DSP design methodology also has fewer and less complicated steps.

DSP High Performance Graph

Spartan Lowers The Cost Even More

In addition to the high capacity XC4000 family, Xilinx DSP now also supports the low cost Spartan family of FPGAs that competes directly with custom gate arrays. Our DSP LogiCORE libraries work with Spartan devices, further reducing the cost per MEGA-MAC in DSP applications. Any Spartan FPGA device is available for less than $20.00 in gate array volumes, and in many applications the S40 can do the work of two high-end DSP processors.

Spartan DSP prices

Design with DSP System-level Tools and Target Xilinx FPGAs

With SystemView by Elanix, it is now possible to specify the DSP algorithm as block a diagram, verify that the algorithm is mathematically correct, and then test the fixed-point implementation using bit-true simulation. The bit-width can be optimized at each stage of the processing to match the system requirements. The Xilinx CORE Generator then implements the design that is specified by the system-level tool.

Xilinx DSP Design Flow

The Xilinx CORE Generator and Smart-IP Technology Produce an Optimized FPGA Design

The DSP cores include a layout or floorplan and their performance and CLB count is specified in a data sheet. The core performance is predictable and independent of FPGA device size. Cores can be placed anywhere in a large device without effecting each others performance.

Add a Xilinx FPGA, Not Multiple Processors

Now it is practical to add a Xilinx FPGA instead of multiple DSP processors for computationally intensive algorithms such as high sample-rate filtering and high-speed FFTs found in communication application, or for the high data rates found in image processing. Use a processor for code-intensive algorithms and low sample rates, but use Xilinx DSP for the high-performance data path that requires hundreds of millions of multiply accumulate operations.

Availability

The Xilinx CORE Generator system, including the DSP LogiCORE libraries, is available now as part of the Xilinx Foundation or Alliance Software Products. For more information about the CORE Generator system visit the Xilinx CORE Generator web page. SystemView by Elanix integrated with Xilinx libraries will be available from Elanix June 1998. The AllianceCORE DSP development boards are available from GV & Associates.

To learn more about the Xilinx DSP solutions, please read the []Xilinx DSP Brochure