San Jose, CA, September 20, 1999—XilinxÒ , Inc. (NASDAQ;XLNX) announced today the first of its new family of in-system programmable (ISP), serial/parallel-load FPGA/CPLD configuration PROMs, the XC1800Ô series. Configuration memories are used for the logic initialization of SRAM-based FPGAs, such as VirtexÔ and SpartanÔ series or SRAM-based CPLDs, such as the new Xilinx CoolRunnerÔ series, or FPGAs. This family, initially ranging from 128 Kbits to 4 Mbits of configuration memory, dramatically increases the range of programmable logic device densities that can be served by a single configuration chip while setting a new standard in ease of use. 

"The XC1800 PROM series demonstrates the Xilinx commitment to industry leadership in PLD configuration memories. No other devices on the market today provide the density, ease-of-use, power, and performance advantages of our XC1800 family of configuration memories," said Evert Wolsheimer, vice president and general manager of the Xilinx CPLD/PROM business unit. 

Unlike many other configuration PROMs in the market today, the entire XC1800 family can be re-programmed in-system, accommodating last-minute design changes and remote reconfiguration without replacing or even removing the PROM from the system. Unlike some competing products, this ISP feature uses IEEE standard 1149.1 Boundary Scan (JTAG) circuitry that allows the XC1800 devices to be integrated into the host system’s JTAG chain, reducing testing and programming overhead for enhanced ease of use. In addition, Boundary Scan capability enables functional testing of the entire system board on which the device is mounted, enhancing the capability of conducting board-level testing. Devices can also be programmed using standard programmers before board mounting. 

Another ease-of-use feature provided in the 1800 family is pinout compatibility, which provides a density migration path between devices in the same package. In addition, density migration is also possible from any 20-pin package to a VQ44 package. This feature eliminates the need for complete board redesign when users migrate to higher PLD densities after board layout. 

The 3.3V XC1800 series is based on the Xilinx advanced low-power CMOS FLASH process. I/O pins accept 5V, 3.3V, and 2.5V signals while driving 3.3V or 2.5V output signals. The devices will be available in a variety of packages, ranging from 20-pin PLCC to 44-pin VQFP. 

XC1800 PROMs will be the industry's first PLD configuration memories with dual-mode configuration capability, enabling unprecedented PLD configuration speeds. In serial mode, data is fed to the PLD bit-wise, in the traditional configuration method. In parallel-load mode, data is passed byte-wise, dramatically reducing the time required to configure FPGAs and CPLDs. The XC1800 family is compatible both with the Express configuration mode of Xilinx Spartan FPGAs and with the SelectMAP configuration mode of Xilinx Virtex FPGAs. 

Power management capabilities feature prominently in the lower-density members of the XC1800 family. Devices with densities up to and including the XC1801Ô have three standby modes, providing increased flexibility to designers in targeting low-power or high-performance applications. The lowest power standby mode makes the XC1801 and lower density devices an attractive choice for battery-dependent applications. 

The XC1800 series of configuration memories are compatible with a variety of PLD families, including Xilinx Spartan, Virtex, and CoolRunner devices. The full XC1800 series is expected to be available in Q4 1999. Volume pricing of the 128-Kbit devices will be $6.97 in 2000.