Memory 

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Application Notes

Title	Size
XAPP201: An Overview of Multiple CAM Designs in Virtex Devices	40 KB
XAPP200: Synthesizable 1.6 Gbytes/s DDR SDRAM Controller	70 KB
XAPP175: High Speed FIFOs In Spartan-II FPGAs	50 KB
XAPP173: Using Block SelectRAM+ Memory in Spartan-II FPGAs	140 KB
XAPP136: Synthesizable 143 MHz ZBT SRAM Interface	30 KB
XAPP134: Synthesizable High Performance SDRAM Controller	100 KB
XAPP130: Using the Virtex Block SelectRAM+	110 KB
XAPP131: 170 MHz FIFOs Using the Virtex Block SelectRAM+	60 KB
XAPP065: XC4000 Series Edge-Triggered and Dual-Port RAM Capability	50 KB
XAPP057: Using SelectRAM Memory in XC4000 Series FPGAs	200 KB
XAPP052: Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators	70 KB
XAPP053: Implementing FIFOs in XC4000 Series RAM	230 KB
XAPP051: Synchronous and Asynchronous FIFO Designs	130 KB

Application Briefs

Title	Size
XBRF001: XC4000E SelectRAM: Flexibility with Speed	20 KB
XBRF003: XC4000E SelectRAM: Maximum Configurability	20 KB

Xcell Articles

Title	Issue
Inferring Virtex Block RAM with Leonardo Spectrum	Q2 '99
Efficient Multi-Channel Serial to Parallel Converter	Q1 '99
Creating Efficient Multi-Tap Shift Registers	Q1 '99
Inferring RAM in Synplify	Q4 '98
XC4000XL FPGAs Interface to SDRAMs at 100 MHz	Q2 '98
A 200 MHz Pulse Generator	Q1 '98
XC4000 Series SelectRAM Memory: Advantages and Uses	Q3 '96
Synchronous RAM Improves System Speed	Q4 '95
Synchronous RAM Timing in the XC4000E FPGA	Q4 '95
Examining XC4000E RAM Capabilities	Q3 '95

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