Xilinx IP Internet Capture

---

IP Internet Capture Documentation
IP Internet Capture Guide (available Dec 1999)

IP Internet Capture
Some programmable logic users report that with so many teams working on FPGA designs, it's difficult to keep track of what IP has been created within a company, what IP has been developed by their own team, what IP needs to be designed. To solve this, the IP Internet Capture tool operates with the cataloging capability of Xilinx CORE Generator system. The IP Internet Capture tool makes design modules created by individual engineers available to others who are using the Xilinx CORE Generator.

The Xilinx IP Internet Capture tool not only provides the ability to browse to and link to the IP sources code, it allows a designer to include and behavioral simulation models, test benches or simulation vector files.

The Xilinx IP Internet Capture tool also requires designers to provide links to documentation. This ensures that all the IP cataloged in the Xilinx CORE Generator system provides a useful starting point for engineers to evaluate whether the IP will meet their reuse needs. This documentation can take the form of a PDF file or an HTML web page

Even though the EDA industry has been addressing the issue of design reuse for several years, it's still a new area for many companies. In some engineering organizations, for example, it's all but impossible for design teams to find out what internal IP already is at their disposal. In others, there is a fundamental distrust of any intellectual property "not invented here" -- whether that IP is from a third party or from another team in the same organization. Still other groups don't want to make the initial effort. The challenge for those who manage design efforts will be to understand that while design reuse initially will cost engineering time and may cut into schedules, it it this investment in time that ultimately will shorten the time required to do subsequent designs.

The IP Internet Capture tool, provides designers with an automated method to identify, capture, and document a core. This core can take the form of synthesizable VHDL or Verilog code, or a fixed function netlist. It even creates a web page with links to download the packaged core. This core can be shared over a customer's network, on an internal or external web site. Once the new module has been captured and posted, other engineers can use standard Internet browsers to download the IP and install it in their copy of the Xilinx CORE Generator system.

By using the IP Internet Capture tool design engineers can quickly package and share IP with other design teams. Because the IP can be downloaded into the Xilinx CORE Generator, other design teams will find it easy to browse the IP catalog and find the IP that they need

Request the IP Internet Capture tool
The Xilinx IP Internet Capture tool will be available for download in December 1999. To be notified when this tool will be available please click the Notify Me link. You will be notified by email when the tools are released.

If you would like to request "Early Access" to the tools, please click on the Send Me An Early Access Version link. The "Early Access version of the IP Internet Capture tool is scheduled for release November 15 1999.