| FOR IMMEDIATE RELEASE
SAN JOSE, Calif., November 1, 1999—Xilinx, Inc. (NASDAQ:XLNX) today announced an Internet-based initiative aimed at helping customers implement designs for reuse and share their intellectual property (IP) internally. The first offerings include the XilinxÒ IP Internet Captureä and IP Remote Interfaceä tools and an FPGA design reuse manual. The IP Internet Capture tool allows customers to easily capture and package intellectual property they have already created for Xilinx FPGAs and share it inside their company with other design teams over the Internet. The IP Remote Interface tool provides customers and third-party developers a method to integrate their own parameter-driven IP with the XilinxÒ CORE Generatorä system. These designs can be distributed or sold over the web in a secure environment. As part of the initiative, Xilinx also announced the publication of the "Xilinx Design Reuse Methodology for ASIC and FPGA Designers" manual, a supplement to the "Reuse Methodology Manual" (RMM) from Synopsys and Mentor Graphics. The Xilinx reuse manual provides guidelines for designers who want a common strategy for reusing intellectual property regardless of whether it was developed for ASICs or for FPGAs. "Xilinx customers have been using million gate Virtex FPGAs for more than a year, and they have benefited from leadership products such as the Xilinx 64-bit, 66-MHz PCI interface core for those devices," said Xilinx CEO Wim Roelandts. "While cores are important to large designs, we also want to help customers leverage the tremendous value of the intellectual property they have developed internally for FPGAs. This initiative goes hand-in-hand with our recent announcement of the new Virtex-E multi-million gate FPGAs and will help customers address challenges of reuse, modular design techniques and team-based design." IP Internet Capture tool The new IP Internet Capture tool, the first of a planned series of programmable logic design reuse software products from Xilinx, provides customers with an automated method to identify, capture, and document a module of synthesizable VHDL or Verilog code, or a fixed function netlist. The IP Internet Capture tool prompts users for reuse information such as module naming and cataloging information, module description, and details about technical support and module source files. The IP Internet Capture tool supports both PDF files and HTML web pages to document cores. The IP Internet Capture tool also allows users to create a directory for copying and creating web files. By creating a web page with links to download the module, the IP Internet Capture tool allows distribution of the intellectual property over a customer's network and internal or external web sites. Once the new module has been captured and posted, other engineers can use standard Internet browsers to download the IP and install it in their copy of the Xilinx CORE Generator system. The IP Internet Capture tool supports all Xilinx FPGA families. IP Remote Interface tool Xilinx also announced the IP Remote Interface tool, which is a new feature of the Xilinx CORE Generator system. Third party Xilinx AllianceCORE partners or customer teams can use the IP Remote Interface tool to create parameter-driven cores. It allows IP designers to create their own graphical user interface and software executables. These applications with customer-specified parameters can then select from a set of fixed net lists, modify generic values in VHDL or Verilog source, or drive algorithmic software code implemented in programming languages such as Perl, C++ or Java. The tool provides a high level of security, and it controls access to IP source code, which can be encrypted or compiled. Xilinx AllianceCORE partners can develop parameter-driven cores that access encrypted source code and then write an encrypted or clear-text netlist. Partners can also control access to their cores by requiring authentication or a password. The IP Remote Interface tool provides the ability to create cores that can access applications over the web. Through the Xilinx CORE Generator, an IP developer can optionally launch an HTTP web application, which provides secure access to the core's source code or an application. This feature provides for authenticated access, source code security and even E-commerce opportunities. "Xilinx has been successful offering customers access to IP such as our PCI cores, BaseBlox, DSP cores and reference designs through the IP Centerä on the Xilinx web site," said Rich Sevcik, senior vice president of software, cores and support at Xilinx. "Providing our AllianceCORE partners and customers with this new reuse capability extends our commitment made a year ago in the Silicon Xpresso initiative to step up use of the Internet to increase the productivity of designers." FPGA Supplement to Reuse Manual The new "Xilinx Design Reuse Methodology for ASIC and FPGA Designers" manual is intended for designers who need to be able to target both ASIC and FPGA architectures with the same RTL code. The Xilinx supplement to the Synopsys and Mentor Graphics RMM manual provides an overview of FPGA system level features and contains general RTL synthesis coding guidelines that have the most impact on improving system performance. "Mentor applauds Xilinx for developing new rules to expand design reuse in the FPGA space," said Pierre Bricaud, director of marketing for the Mentor Graphics IP Division (Beaverton, Ore.). "Mentor, Synopsys and Xilinx are making great strides in facilitating design reuse, which should have a tremendous impact on the electronics industry." "I'm very pleased that Xilinx has taken the initiative to show how the RMM design rules can be extended to system-on-chip design with FPGAs," said Mike Keating, vice president of engineering at Synopsys and co-author of the Synopsys-Mentor RMM manual. "I've always felt that design reuse is built upon the discipline of good design, and that much of this discipline is universal. Having a unified approach, whether the implementation is ASIC or FPGA, will certainly help the industry in meeting the system-on-chip challenge." "With more designers turning to large FPGAs like Xilinx Virtex devices, IP blocks should be designed for reusability in FPGAs as well as ASICs if designers are to maintain flexibility in choice of implementation technology," said Janick Bergeron, vice president at Qualis Design Corp (Lake Oswego, Ore). "Reuse applies just as much to FPGA as it does to ASIC design, and can be similarly accomplished through good coding style and sound design practice." Availability The "Xilinx Design Reuse Methodology for ASIC and FPGA Designers" manual is now published on the new design reuse section of the IP Center. The IP Internet Capture and IP Remote Interface tools will be available from the site in December. The Xilinx IP Center has long been a resource offering access to complete IP solutions. Design reuse is the latest addition to the Xilinx list of IP solutions. Xilinx is the leading innovator of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquartered in San Jose, Calif., Xilinx invented the field programmable gate array (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to reduce significantly the time required to develop products for the computer, peripheral, telecommunications, networking, industrial control, instrumentation, high-reliability/military, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com. Other brands or product names are trademarks or registered trademarks of their respective owners. #9963
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